Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10991523
    Abstract: A keyboard device includes a base plate and a plurality of keyswitches disposed on the base plate. At least one of the keyswitches includes a keycap, two linkages, and two magnetic attraction members. The linkages are connected between the base plate and the keycap and configured to guide the movements of the keycap toward and away from the base plate. The magnetic attraction members are rotatably connected to the linkages, respectively, and are configured to attract each other. When the magnetic attraction members abut against each other, the keycap is at a highest position relative to the base plate. When the keycap moves toward the base plate from the highest position, the magnetic attraction members are separated from each other.
    Type: Grant
    Filed: December 25, 2018
    Date of Patent: April 27, 2021
    Assignee: Chicony Electronics Co, , Ltd.
    Inventors: Shin-Chin Weng, Chun-Chieh Chan, Chao-Chin Hsieh, Chih-Feng Chen
  • Publication number: 20210119024
    Abstract: A semiconductor device and method for making the semiconductor device comprising a flash memory cell is provided. In accordance with some embodiments, the method includes: patterning a first gate material layer and a gate insulating film over a substrate, the first gate material layer comprising a first gate material, the gate insulating film disposed on the first gate material layer; forming a second gate material layer over the substrate, the gate insulating film, and side walls of the first gate material layer, the second gate material layer comprising a second gate material; etching the second gate material layer to expose the substrate and the gate insulating film and provide a portion of the second gate material layer along each of the side walls of the first gate material layer; and etching the gate insulating film and the first gate material layer so as to form a plurality of gate structures.
    Type: Application
    Filed: December 9, 2020
    Publication date: April 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Hung Lin, Chun-Chieh Mo, Shih-Chi Kuo
  • Publication number: 20210111027
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu LIN, Chi-Yu CHOU, Hsien-Ming LEE, Huai-Tei YANG, Chun-Chieh WANG, Yueh-Ching PAI, Chi-Jen YANG, Tsung-Ta TANG, Yi-Ting WANG
  • Publication number: 20210111625
    Abstract: The disclosure provides a power conversion circuit with a multi-function pin and a multi-function setting method thereof. The multi-function pin is coupled to an external setting circuit. The power conversion circuit includes a first function circuit, a second function circuit, and a judging circuit. The first function circuit is coupled to the multi-function pin. The second function circuit is coupled to the multi-function pin. The judging circuit is coupled to the multi-function pin, the first function circuit, and the second function circuit. The judging circuit provides a setting current to the multi-function pin, so that the external setting circuit generates a voltage according to the setting current. The judging circuit judges the type of external setting circuit according to voltage so as to activate the first function circuit or the second function circuit accordingly.
    Type: Application
    Filed: August 12, 2020
    Publication date: April 15, 2021
    Applicant: uPI Semiconductor Corp.
    Inventors: Chih-Lien Chang, Chun-Chieh Wang
  • Patent number: 10976958
    Abstract: A method for controlling a storage device is provided. The method may include: transmitting an initial command conforming to a first communications protocol and a data payload including a command parameter conforming to a second communications protocol to the storage device; transmitting a setting command conforming to the first communications protocol to the storage device; transmitting a confirmation command conforming to the first communications protocol to the storage device; and according to a data payload corresponding to the confirmation command, confirming whether the initial command, the setting command, and the confirmation command are successfully executed.
    Type: Grant
    Filed: July 4, 2018
    Date of Patent: April 13, 2021
    Assignee: Silicon Motion, Inc.
    Inventor: Chun-Chieh Chen
  • Publication number: 20210105018
    Abstract: A signal converting apparatus includes a comparing device, a first digital-slope quantizer, and a second digital-slope quantizer. The comparing device has a first input terminal and a second input terminal for receiving a received signal and an adjustable reference voltage respectively, and for generating an output signal at an output port. The first digital-slope quantizer is coupled to the output port and the second input terminal for generating a first set of digital signals to monotonically adjust the adjustable reference voltage at the second input terminal during a first phase according to a first quantization unit. The second digital-slope quantizer is coupled to the output port and the second input terminal for generating a second set of digital signals to monotonically adjust the adjustable reference voltage at the second input terminal during a second phase after the first phase according to a second quantization unit.
    Type: Application
    Filed: October 7, 2020
    Publication date: April 8, 2021
    Applicant: TRON FUTURE TECH INC.
    Inventors: Yu-Jiu WANG, Chun-Chieh PENG, Ta-Shun CHU
  • Patent number: 10971602
    Abstract: An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Shun Liao, Huai-Tei Yang, Chun Chieh Wang, Yueh-Ching Pai, Chun-I Wu
  • Publication number: 20210098617
    Abstract: A semiconductor device includes an active layer having an active region, a source electrode, a drain electrode, a gate electrode, a source metal layer, a drain metal layer, and a source pad. The source metal layer and the drain metal layer are electrically connected to the source electrode and the drain electrode, respectively. An orthogonal projection of the drain metal layer on the active layer each forms a drain metal layer region. The source pad is electrically connected to the source metal layer. An orthogonal projection of the source pad on the active layer forms a source pad region overlapping the drain metal layer. An area of an overlapping region between the source pad region and the drain metal layer region is smaller than or equal to 40% of an area of the drain metal layer region.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: Li-Fan LIN, Chun-Chieh YANG, Ying-Chen LIU
  • Publication number: 20210096242
    Abstract: An underwater ultrasonic device includes a curvilinear ultrasonic transducer and a plurality of straight linear ultrasonic transducers. The straight linear ultrasonic transducers are disposed with respect to the curvilinear ultrasonic transducer. A first angle is included between the straight linear ultrasonic transducers. One of the curvilinear ultrasonic transducer and the straight linear ultrasonic transducer is configured to transmit a plurality of ultrasonic signals. Another one of the curvilinear ultrasonic transducer and the straight linear ultrasonic transducer is configured to receive a plurality of reflected signals of the ultrasonic signals.
    Type: Application
    Filed: September 11, 2020
    Publication date: April 1, 2021
    Inventors: Fu-Sheng Jiang, Chun-Chieh Wang, Yi-Hsiang Chan, Heng-Yi Shiu, Hsin-Chih Liu
  • Patent number: 10961616
    Abstract: This disclosure relates to the field of display fabrication technologies, and discloses a fine mask support frame, a fine mask, and a method for fabricating the same. The fine mask support frame includes: a plurality of bezels surrounding a mask area, wherein adjustment openings are arranged on at least one pair of bezels arranged opposite to each other, and at least one adjustment piece is arranged on each of the adjustment openings, wherein the adjustment piece is configured to adjust a shape of a corresponding adjustment opening to thereby adjust deformation of the mask area.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: March 30, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Zhiming Lin, Baojun Li, Jian Zhang, Pu Sun, Chun Chieh Huang
  • Publication number: 20210089111
    Abstract: A heat dissipation apparatus with energy-saving effect is coupled to an operation unit, and the heat dissipation apparatus includes a control unit and a drive circuit. The control unit determines whether the operation unit enters an energy-saving mode according to a first signal provided by the operation unit. The control unit shields a plurality of second signals provided to the drive circuit according to the energy-saving mode. The drive circuit does not drive the heat dissipation unit and the heat dissipation unit enters an inertia deceleration.
    Type: Application
    Filed: April 18, 2020
    Publication date: March 25, 2021
    Inventors: Chia-Feng WU, Po-Hui SHEN, Chien-Sheng LIN, Chun-Chieh TSAI, Chia-Wei HSU, Rou-Sheng WANG
  • Publication number: 20210091229
    Abstract: A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion.
    Type: Application
    Filed: September 22, 2019
    Publication date: March 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Ching Cheng, Chun-Chieh Lu, Hung-Li Chiang, Tzu-Chiang Chen
  • Patent number: 10955517
    Abstract: An underwater ultrasonic device includes at least one first ultrasonic transducer and at least one second ultrasonic transducer. The first ultrasonic transducer is configured to transmit a plurality of ultrasonic signals and the second ultrasonic transducer is configured to receive a plurality of reflected signals of the ultrasonic signals. The first ultrasonic transducer and the second ultrasonic transducer are disposed with respect to each other. One of the first ultrasonic transducer and the second ultrasonic transducer is curvilinear and another one of the first ultrasonic transducer and the second ultrasonic transducer is curvilinear or straight linear.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: March 23, 2021
    Assignee: Qisda Corporation
    Inventors: Fu-Sheng Jiang, Chun-Chieh Wang
  • Publication number: 20210076812
    Abstract: Buffing of a footwear component allows for an alteration of the component surface to achieve an intended surface for aesthetics and/or manufacturing purposes. The buffing is performed in a system having a vision module, a sidewall buffing module, an up surface buffing module, and a down surface buffing module. Each of the buffing modules are adapted for the unique shape and sizes of a footwear component to effectively and automatically buff the footwear component.
    Type: Application
    Filed: September 15, 2020
    Publication date: March 18, 2021
    Inventors: CHUN-CHIEH CHEN, YI-MIN CHEN, CHIA-HUNG LIN, HSIEN-KUANG WU, HUNG-YU WU
  • Publication number: 20210083082
    Abstract: A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Chao-Ching Cheng, Hung-Li Chiang, Chun-Chieh Lu, Ming-Yang Li, Tzu- Chiang Chen
  • Publication number: 20210082801
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a capacitor structure, and a conductive contact. The semiconductor substrate has at least one semiconductor fin thereon. The gate structure is disposed across the semiconductor fin. The capacitor structure is disposed on the gate structure. The capacitor structure includes a ferroelectric layer and a first metal layer disposed on the ferroelectric layer. The capacitor structure is sandwiched between the conductive contact and the gate structure.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Ho, Chun-Chieh Lu, Chih-Sheng Chang
  • Publication number: 20210076781
    Abstract: Buffing of a footwear component allows for an alteration of the component surface to achieve an intended surface for aesthetics and/or manufacturing purposes. The buffing is performed in a system having a vision module, a sidewall buffing module, an up surface buffing module, and a down surface buffing module. Each of the buffing modules are adapted for the unique shape and sizes of a footwear component to effectively and automatically buff the footwear component.
    Type: Application
    Filed: September 15, 2020
    Publication date: March 18, 2021
    Inventors: CHUN-CHIEH CHEN, YI-MIN CHEN, CHIA-HUNG LIN, HSIEN-KUANG WU, HUNG-YU WU
  • Publication number: 20210079925
    Abstract: A data processing method is proposed, including: sensing, via at least one sensing portion, target information of a target device; receiving and processing, via an electronic device, the target information of the sensing portion to form feature information; processing, via the electronic device, the feature information into a label matrix, and establishing, via an artificial intelligence training method, a target model based on the label matrix; and after the electronic device captures real-time information of the target device, predicting, via the target model, a life limit of the target device, wherein a content of the target information is corresponding to a content of the real-time information. Thus, a good target model is constituted and is advantageous in training artificial intelligence by processing the feature information into the label matrix.
    Type: Application
    Filed: February 18, 2020
    Publication date: March 18, 2021
    Inventors: Ming-Hsiang Hsu, Chun-Chieh Wang, Hung-Tsai Wu
  • Publication number: 20210076780
    Abstract: Buffing of a footwear component allows for an alteration of the component surface to achieve an intended surface for aesthetics and/or manufacturing purposes. The buffing is performed in a system having a vision module, a sidewall buffing module, an up surface buffing module, and a down surface buffing module. Each of the buffing modules are adapted for the unique shape and sizes of a footwear component to effectively and automatically buff the footwear component.
    Type: Application
    Filed: September 15, 2020
    Publication date: March 18, 2021
    Inventors: CHUN-CHIEH CHEN, YI-MIN CHEN, CHIA-HUNG LIN, HSIEN-KUANG WU, HUNG-YU WU
  • Patent number: D914687
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: March 30, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Jen-Ting Wei, Chen-Cheng Wang, Chun-Chieh Chen