Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210082801
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a capacitor structure, and a conductive contact. The semiconductor substrate has at least one semiconductor fin thereon. The gate structure is disposed across the semiconductor fin. The capacitor structure is disposed on the gate structure. The capacitor structure includes a ferroelectric layer and a first metal layer disposed on the ferroelectric layer. The capacitor structure is sandwiched between the conductive contact and the gate structure.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Ho, Chun-Chieh Lu, Chih-Sheng Chang
  • Publication number: 20210076779
    Abstract: Buffing of a footwear component allows for an alteration of the component surface to achieve an intended surface for aesthetics and/or manufacturing purposes. The buffing is performed in a system having a vision module, a sidewall buffing module, an up surface buffing module, and a down surface buffing module. Each of the buffing modules are adapted for the unique shape and sizes of a footwear component to effectively and automatically buff the footwear component.
    Type: Application
    Filed: September 15, 2020
    Publication date: March 18, 2021
    Inventors: CHUN-CHIEH CHEN, YI-MIN CHEN, CHIA-HUNG LIN, HSIEN-KUANG WU, HUNG-YU WU
  • Patent number: 10950524
    Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer, a first source pad, and a first drain pad. The source electrode, the drain electrode, and the gate electrode are disposed on an active region of the active layer. The first insulating layer is disposed on the source electrode, the drain electrode, and the gate electrode. The first source pad and the first drain pad are disposed on the first insulating layer and the active region. The first source pad includes a first source body and a first source branch. The first source branch is electrically connected to the first source body and disposed on the source electrode. The first drain pad includes a first drain body and a first drain branch. The first drain branch is electrically connected to the first drain body and disposed on the drain electrode.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: March 16, 2021
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Li-Fan Lin, Chun-Chieh Yang
  • Publication number: 20210074812
    Abstract: A semiconductor device includes a fin structure, a two-dimensional (2D) material channel layer, a ferroelectric layer, and a metal layer. The fin structure extends from a substrate. The 2D material channel layer wraps around at least three sides of the fin structure. The ferroelectric layer wraps around at least three sides of the 2D material channel layer. The metal layer wraps around at least three sides of the ferroelectric layer.
    Type: Application
    Filed: October 30, 2020
    Publication date: March 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh LU, Meng-Hsuan HSIAO, Tung-Ying LEE, Ling-Yen YEH, Chih-Sheng CHANG, Carlos H. DIAZ
  • Patent number: 10943909
    Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: March 9, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
  • Patent number: 10939945
    Abstract: A minimally invasive bone fracture positioning device includes a sleeve, a movable unit, and a support. The sleeve includes an alignment portion located on a longitudinal axis of the sleeve. The movable unit includes a positioning portion. The positioning portion is located on the longitudinal axis and is spaced from the alignment portion. The movable unit is mounted in a radial direction of the sleeve. The movable unit is slideable relative to the sleeve along the longitudinal axis. A support is coupled to the sleeve and the movable unit. The movable unit is spaced from the sleeve by the support.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: March 9, 2021
    Assignee: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTRE
    Inventors: Yue-Jun Wang, Chih-Hao Chang, Shih-Hua Huang, Chih-Lung Lin, Tung-Lin Tsai, Chun-Chieh Tseng, Li-Wen Weng
  • Publication number: 20210067062
    Abstract: Provided is an electronic device and an electric energy conversion method. The electronic device includes at least one moving component, a transducer system, a charging and discharging system, and a power supply system. The transducer system has at least one piezoelectric membrane and a storage unit. The at least one piezoelectric membrane is disposed on the at least one moving component, and the storage unit is electrically coupled to the at least one piezoelectric membrane. The charging and discharging system is electrically coupled to the at least one moving component and the transducer system. The power supply system is electrically coupled to the at least one moving component, the transducer system, and the charging and discharging system to provide main energy. The at least one moving component starts to operate, the at least one moving component leads the at least one piezoelectric membrane to deform elastically to generate assisting charges.
    Type: Application
    Filed: August 25, 2020
    Publication date: March 4, 2021
    Applicant: Coretronic Corporation
    Inventors: Jui-Ta Liu, Chun-Chieh Wang, Chih-Hsiang Li, Kuo-Liang Peng
  • Publication number: 20210066160
    Abstract: A coating method applied to perform coating with liquid metal thermal grease and a heat dissipation module are provided. The coating method includes: providing liquid metal thermal grease on a surface of an electronic element, and scraping the liquid metal thermal grease by a scraper, to coat the surface of the electronic element with the liquid metal thermal grease. A surface of the scraper is roughened. According to the coating method, the surface of the electronic element is evenly coated with the liquid metal thermal grease effectively.
    Type: Application
    Filed: July 17, 2020
    Publication date: March 4, 2021
    Inventors: Chia-Chang LEE, Chun-Chieh WONG, Cheng-Yu WANG, Tai-Min HSU, Yao-Jen CHANG
  • Publication number: 20210066627
    Abstract: A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.
    Type: Application
    Filed: April 1, 2020
    Publication date: March 4, 2021
    Inventors: Chao-Ching Cheng, Tzu-Ang Chao, Chun-Chieh Lu, Hung-Li Chiang, Tzu-Chiang Chen, Lain-Jong Li
  • Patent number: 10937910
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure and a gate spacer formed on a sidewall surface of the gate structure. The semiconductor structure also includes a first source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate spacer, and a second S/D epitaxial layer formed over the first S/D epitaxial layer. A top surface of the second S/D layer is higher than a top surface of the first S/D epitaxial layer.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chun-Chieh Wang, Yu-Ting Lin, Yueh-Ching Pai, Shih-Chieh Chang, Huai-Tei Yang
  • Publication number: 20210053180
    Abstract: A chemical mechanical planarization (CMP) tool includes a platen and a polishing pad attached to the platen, where a first surface of the polishing pad facing away from the platen includes a first polishing zone and a second polishing zone, where the first polishing zone is a circular region at a center of the first surface of the polishing pad, and the second polishing zone is an annular region around the first polishing zone, where the first polishing zone and the second polishing zone have different surface properties.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Inventors: Michael Yen, Kao-Feng Liao, Hsin-Ying Ho, Chun-Wen Hsiao, Sheng-Chao Chuang, Ting-Hsun Chang, Fu-Ming Huang, Chun-Chieh Lin, Peng-Chung Jangjian, Ji James Cui, Liang-Guang Chen, Chih Hung Chen, Kei-Wei Chen
  • Publication number: 20210052584
    Abstract: The present invention features a compound of formula I: or a pharmaceutically acceptable salt thereof, where R1, R2, R3, W, X, Y, Z, n, o, p, and q are defined herein, for the treatment of CFTR mediated diseases, such as cystic fibrosis. The present invention also features pharmaceutical compositions, method of treating, and kits thereof.
    Type: Application
    Filed: March 31, 2020
    Publication date: February 25, 2021
    Applicant: Vertex Pharmaceuticals Incorporated
    Inventors: Mark Thomas Miller, Corey Anderson, Vijayalaksmi Arumugam, Brian Richard Bear, Hayley Marie Binch, Jeremy J. Clemens, Thomas Cleveland, Erica Conroy, Timothy Richard Coon, Bryan A. Frieman, Peter Diederik Jan Grootenhuis, Raymond Stanley Gross, Sara Sabina Hadida-Ruah, Haripada Khatuya, Pramod Virupax Joshi, Paul John Krenitsky, Chun-Chieh Lin, Gulin Erdogan Marelius, Vito Melillo, Jason McCartney, Georgia McGaughey Nicholls, Fabrice Jean Denis Pierre, Alina Silina, Andreas P. Termin, Johnny Uy, Jinglan Zhou
  • Publication number: 20210057290
    Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 25, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Shiang LIN, Chia-Cheng HO, Chun-Chieh LU, Cheng-Yi PENG, Chih-Sheng CHANG
  • Patent number: 10930769
    Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Cheng-Yi Peng, Chien-Hsing Lee, Ling-Yen Yeh, Chih-Sheng Chang, Carlos H. Diaz
  • Patent number: 10928869
    Abstract: A heat dissipation module including a chamber, a first cooling member, and a barrier part is provided. The chamber has an accommodating space, at least one inlet, and at least one outlet. The at least one inlet is disposed in a first side wall of the chamber and communicates with the accommodating space. The at least one outlet is disposed in a second side wall of the chamber away from the at least one inlet and communicates with the accommodating space. The first cooling member is disposed in the accommodating space. The first cooling member has a guiding surface which extends obliquely upward. The barrier part is disposed outside the guiding surface of the first cooling member and has at least one through hole.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: February 23, 2021
    Assignee: Acer Incorporated
    Inventors: Chun-Chieh Wang, Wen-Neng Liao, Cheng-Wen Hsieh, Wei-Chin Chen, Jau-Han Ke
  • Patent number: 10928130
    Abstract: A drying system and a drying method for a cleaning solution on a mask are disclosed. The drying system includes: a drying chamber having a first side wall and a second side wall arranged opposite to the first side wall; a plurality of first air knives on the first side wall and the second side wall for air-drying a cleaned mask; and a separation device for allowing a mask strip and a supporting and shielding strip to move away from each other at a spatial intersection region to increase a spacing between the mask strip and the supporting and shielding strip at the spatial intersection region, when the plurality of first air knives are air-drying the cleaned mask.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: February 23, 2021
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhiming Lin, Zhen Wang, Baojun Li, Zhi Yin, Chun-Chieh Huang
  • Patent number: 10925138
    Abstract: A flicker-free linear LED drive circuit is disclosed. The flicker-free linear LED drive circuit converts the input voltage of the external power supply to form an output current to the LED. The flicker-free linear LED drive circuit includes a measuring module, a regulating module and a rectifier module. The flicker-free linear LED drive circuit is characterized in that the measuring module is configured to measure the phase angle of the input voltage after full-wave rectification; the regulating module is used to form the complex voltage signal according to the measurement signal in the voltage waveform of the regulating module for the half-wave period, the conduction angle range formed at the fixed power is used as the basis for electrical conduction in the half-wave period of the input voltage.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: February 16, 2021
    Assignee: UNITY OPTO TECHNOLOGY CO., LTD.
    Inventors: Chih-Hsien Wu, Kai-Cheng Chuang, Chun-Chieh Kuo, Yu-Hsien He
  • Patent number: 10923709
    Abstract: The disclosure describes an exemplary binding layer formed on Aluminum (Al) substrate that binds the substrate with a coated material. Additionally, an extended form of the binding layer is described. By making a solution containing Al-transition metal elements-P—O, the solution can be used in slurry making (the slurry contains active materials) in certain embodiments. The slurry can be coated on Al substrate followed by heat treatment to form a novel electrode. Alternatively, in certain embodiments, the solution containing Al-transition metal elements-P—O can be mixed with active material powder, after heat treatment, to form new powder particles bound by the binder.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: February 16, 2021
    Assignee: Changs Ascending Enterprise, Co., Ltd.
    Inventors: Chun-Chieh Chang, Tsun Yu Chang
  • Publication number: 20210040349
    Abstract: A method of producing a fouling-proof structure, comprising steps of a) coating an alcohol-resistant combination on a substrate and then drying the alcohol-resistant combination at 80-160° C. to form an alcohol-resistant layer; and b) coating a water-based fouling-proof combination on the alcohol-resistant layer and then drying the water-based fouling-proof combination above 140° C. to form a water-based fouling-proof layer, wherein the alcohol-resistant layer is formed by curing an alcohol-resistant combination, and the alcohol-resistant combination comprises polyurethane resin, wherein the water-based fouling-proof layer is formed by curing a water-based fouling-proof combination, and the water-based fouling-proof combination comprises polyurethane resin, water, polymerized siloxanes, water-based PTFE and silicone oil.
    Type: Application
    Filed: March 6, 2020
    Publication date: February 11, 2021
    Inventors: CHING-HSIANG CHANG, KUO-HSING YEH, CHUN-CHIEH WANG
  • Publication number: 20210040332
    Abstract: A fouling-proof structure is applicable to synthetic leather or fabric and it includes an alcohol-resistant layer; and a water-based fouling-proof layer disposed on the alcohol-resistant layer, wherein the alcohol-resistant layer is formed by curing an alcohol-resistant combination, and the alcohol-resistant combination comprises polyurethane resin, wherein the water-based fouling-proof layer is formed by curing a water-based fouling-proof combination, and the water-based fouling-proof combination comprises polyurethane resin, water, polymerized siloxanes, water-based PTFE and silicone oil.
    Type: Application
    Filed: March 6, 2020
    Publication date: February 11, 2021
    Inventors: CHING-HSIANG CHANG, KUO-HSING YEH, CHUN-CHIEH WANG