Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210038697
    Abstract: Hepatitis E vims (HEV)-based virus like particles (VLP) made with a modified capsid protein containing at least a portion of open reading frame 2 (ORF2) protein and encapsulated insulin protein or insulin encoding nucleic acid are provided. Also provided are methods of targeted delivery of insulin using the HEV VLP.
    Type: Application
    Filed: March 13, 2019
    Publication date: February 11, 2021
    Inventors: R. Holland CHENG, Chun Chieh Chen, Mohammad Ali Baikoghli
  • Patent number: 10914807
    Abstract: A point stick module has a sensing device, a rank unit and a signal processing device. The sensing device outputs multiple sensing signals in response to operations done by a user. The rank unit provides a rank signal to represent a rank of the sensing device. The signal processing device is coupled to the sensing device and the rank unit to receive the multiple sensing signals and the rank signal, wherein the signal processing device selects a parameter according to the rank signal.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 9, 2021
    Assignee: Elan Microelectronics Corporation
    Inventor: Chun-Chieh Huang
  • Patent number: 10916473
    Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: February 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hao Chung, Chang-Sheng Lin, Kuo-Feng Huang, Li-Chieh Wu, Chun-Chieh Lin
  • Publication number: 20210036147
    Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.
    Type: Application
    Filed: May 31, 2020
    Publication date: February 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Wang, Sheng-Wei Yeh, Yueh-Ching Pai, Chi-Jen Yang
  • Publication number: 20210035969
    Abstract: A high-voltage circuitry device is provided. The high-voltage circuitry device includes a high-voltage transistor, a protection component and a feedback component. The high-voltage transistor has a gate, a drain and a source. The protection component is coupled between the source of the high-voltage transistor and the ground. When a current corresponding to an electrostatic discharge (ESD) event flows through the drain of the high-voltage transistor, the current flows from the drain of the high-voltage transistor to the ground through the high-voltage transistor and the protection component. The feedback component is coupled between the protection component, the ground and the gate of the high-voltage transistor. When the ESD event occurs, the feedback component enables the high-voltage transistor to stay on a turned-on state to pass the current.
    Type: Application
    Filed: November 18, 2019
    Publication date: February 4, 2021
    Inventors: Yi-Hao CHEN, Tsu-Yi WU, Chih-Hsun LU, Po-An CHEN, Chun-Chieh LIU
  • Patent number: 10910491
    Abstract: A semiconductor device includes an active layer having an active region, a source electrode, a drain electrode, a gate electrode, a source metal layer, a drain metal layer, and a source pad. The source metal layer and the drain metal layer are electrically connected to the source electrode and the drain electrode, respectively. An orthogonal projection of the drain metal layer on the active layer each forms a drain metal layer region. The source pad is electrically connected to the source metal layer. An orthogonal projection of the source pad on the active layer forms a source pad region overlapping the drain metal layer. An area of an overlapping region between the source pad region and the drain metal layer region is smaller than or equal to 40% of an area of the drain metal layer region.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: February 2, 2021
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Li-Fan Lin, Chun-Chieh Yang, Ying-Chen Liu
  • Patent number: 10910468
    Abstract: Provided is a capacitor structure including a substrate, a cup-shaped lower electrode, a top supporting layer, a capacitor dielectric layer, and an upper electrode. The cup-shaped lower electrode is located on the substrate. The top supporting layer surrounds the upper portion of the cup-shaped lower electrode. The top supporting layer includes a high-k material. Surfaces of the cup-shaped lower electrode and the top supporting layer are covered by the capacitor dielectric layer. A surface of the capacitor dielectric layer is covered by the upper electrode.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: February 2, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Cheol Soo Park, Ming-Tang Chen, Chun-Chieh Wang
  • Patent number: 10896220
    Abstract: A method of searching an image file includes: utilizing a login module to log in a user account; utilizing an input module to store an image file at a predetermined location; utilizing an information capturing module to capture at least one image information of the image file stored at the predetermined location; utilizing an index building module to build at least one index tag corresponding to the image file according to the at least one image information captured by the information capturing module; utilizing a searching module to receive at least one searching condition so as to search the at least one index tag according to the at least one searching condition; and utilizing a display module to display a searching result corresponding to the image file when the at least one index tag matches with the at least one searching condition.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: January 19, 2021
    Assignee: AVISION INC.
    Inventors: Chun-Chieh Liao, Chun-Ping Huang, Hung-Jen Lin
  • Publication number: 20210011525
    Abstract: An electronic device including a first body, a second body, a hinge structure, an electronic assembly and a linkage mechanism is provided. The first body and the second body are pivoted to each other through the hinge structure. The electronic assembly is disposed on the first body. The linkage mechanism is disposed in the first body and connected between the hinge structure and the electronic assembly. When the second body is closed to the first body, the electronic assembly is hidden between the first body and the second body. When the second body is opened relative to the first body with an opening angle less than a predetermined angle, the hinge structure does not drive the linkage mechanism. When the second body is opened relative to the first body with the opening angle not less than the predetermined angle, the hinge structure drives the linkage mechanism and the linkage mechanism drives the electronic assembly to be opened relative to the first body.
    Type: Application
    Filed: July 7, 2020
    Publication date: January 14, 2021
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Che-Hsien Lin, Che-Hsien Chu, Ko-Yen Lu, Chun-Chieh Chen, Chen-Ming Lee, Yi-Hung Chen, I-Chien Huang
  • Publication number: 20210013033
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 14, 2021
    Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Hung-Yi Huang, Chun Chieh Wang, Yu-Ting Lin
  • Publication number: 20210011643
    Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 14, 2021
    Inventors: Tsung-Chieh Yang, Chun-Chieh Kuo, Ching-Hui Lin, Yang-Chih Shen
  • Publication number: 20210005734
    Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Inventors: Chun-Chieh LU, Carlos H. DIAZ, Chih-Sheng CHANG, Cheng-Yi PENG, Ling-Yen YEH
  • Patent number: 10886320
    Abstract: An image-sensor device includes a substrate including a pixel region and a logic region. A logic transistor is disposed in the logic region and is surrounded by a logic isolation feature. A radiation-sensing region is disposed in the pixel region of the substrate. An epitaxial pixel isolation feature is disposed in the pixel region and surrounds the radiation-sensing region. A doped region with a same doping polarity as the radiation-sensing region is located between a bottom of the radiation-sensing region and the back surface of the substrate. The epitaxial pixel isolation feature is in direct contact with the doped region. The doped region extends continuously under the pixel region and the logic region. The epitaxial pixel isolation feature is in direct contact with the doped region, and the logic isolation feature is spaced apart from the doped region.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: January 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-I Hsu, Feng-Chi Hung, Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu
  • Patent number: 10885962
    Abstract: Vertical memory cells and memory devices using the same are disclosed. In one example, a memory cell formed on a backend layer over a substrate is disclosed. The memory cell includes: a first electrode, a second electrode and a magnetic tunnel junction. The first electrode has sidewalls and a bottom surface disposed over the backend layer. The second electrode has sidewalls and a bottom surface in contact with the backend layer. The magnetic tunnel junction is formed between the first electrode and the second electrode. The magnetic tunnel junction is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: January 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Mo, Shih-Chi Kuo
  • Publication number: 20200412280
    Abstract: An apparatus and a method for monitoring the relative relationship between the wafer and the chuck is provided, especially for monitoring whether the wafer is sticky on the chuck when the wafer is de-chucked. The lift pins may be extended outside the chuck to separate the wafer and the chuck when the wafer is de-chucked. By detecting the capacitance between the de-chucked wafer and the chuck, especially by comparing the detected capacitance with the capacitance that the wafer is held by the chuck, one may determine whether the wafer is sticky on the chuck, or even whether the wafer is properly supported by the lift pins. Accordingly, an early alarm may be issued if the wafer is sticky or improperly removed. Besides, by controlling a switch electrically connected to a lift pin that contacted the wafer, the charges at the wafer may be eliminated.
    Type: Application
    Filed: September 10, 2020
    Publication date: December 31, 2020
    Inventors: Te-Min Wang, Yu-Ho Ni, Chun-Chieh Lin, Chien-Chung Hou, Cheng-Mao Chien
  • Patent number: 10879396
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate stack to partially cover a semiconductor structure. The method also includes forming a first semiconductor material over the semiconductor structure. The method further includes forming a second semiconductor material over the first semiconductor material. In addition, the method includes forming a third semiconductor material over the second semiconductor material. The first semiconductor material and the third semiconductor material together surround the second semiconductor material. The second semiconductor material has a greater dopant concentration than that of the first semiconductor material or that of the third semiconductor material.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Chun-Chieh Wang, Cheng-Han Lee, Shih-Chieh Chang
  • Patent number: 10879297
    Abstract: An image sensor device includes a pixel array, a control circuit, an interconnect structure, and a conductive layer. The pixel array is disposed on a device substrate within a pixel region. The control circuit disposed on the device substrate within a circuit region, the control circuit being adjacent and electrically coupled to the pixel array. The interconnect structure overlies and electrically connects the control circuit and the pixel array. The interconnect structure includes interconnect metal layers separated from each other by inter-metal dielectric layers and vias that electrically connect between metal traces of the interconnect layers. The conductive layer disposed over the interconnect structure and electrically connected to the interconnect structure by an upper via disposed through an upper inter-metal dielectric layer therebetween. The conductive layer extends laterally within outermost edges of the interconnect structure and within the pixel region and the circuit region.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-De Wang, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Jeng-Shyan Lin
  • Patent number: 10879380
    Abstract: A semiconductor device and method for making the semiconductor device comprising a flash memory cell is provided. In accordance with some embodiments, the method includes: patterning a first gate material layer and a gate insulating film over a substrate, the first gate material layer comprising a first gate material, the gate insulating film disposed on the first gate material layer; forming a second gate material layer over the substrate, the gate insulating film, and side walls of the first gate material layer, the second gate material layer comprising a second gate material; etching the second gate material layer to expose the substrate and the gate insulating film and provide a portion of the second gate material layer along each of the side walls of the first gate material layer; and etching the gate insulating film and the first gate material layer so as to form a plurality of gate structures.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Hung Lin, Chun-Chieh Mo, Shih-Chi Kuo
  • Patent number: 10879124
    Abstract: The present disclosure describes an exemplary fabrication method of a p-type fully strained channel that can suppress the formation of {111} facets during a silicon germanium epitaxial growth. The exemplary method includes the formation of silicon epitaxial layer on a top, carbon-doped region of an n-type region. A recess is formed in the silicon epitaxial layer via etching, where the recess exposes the top, carbon-doped region of the n-type region. A silicon seed layer is grown in the recess, and a silicon germanium layer is subsequently epitaxially grown on the silicon seed layer to fill the recess. The silicon seed layer can suppress the formation of growth defects such as, for example, {111} facets, during the silicon germanium epitaxial layer growth.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Wang, Huai-Tei Yang, Zheng-Yang Pan, Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee
  • Patent number: 10879240
    Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a fin structure extending above a substrate. The fin structure includes a channel region, a portion of the channel region is made of silicon germanium (SiGe), and the silicon germanium (SiGe) has a gradient germanium (Ge) concentration. The FinFET device structure includes a gate structure formed on the channel region of the fin structure.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Wang, Zheng-Yang Pan, Shih-Chieh Chang, Yi-Min Huang, Shahaji B. More, Tsung-Lin Lee