Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10217998
    Abstract: Various embodiments of a novel chemical synthesis route for lithium ion battery applications are focused on the synthesis of a new active material using NMC (Lithium Nickel Manganese Cobalt Oxide) as the precursor for a phosphate material having a layered crystal structure. Partial phosphate generation in the layer structured material stabilizes the material while maintaining the large capacity nature of the layer structured material.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: February 26, 2019
    Assignee: CHANGS ASCENDING ENTERPRISE CO., LTD.
    Inventors: Chun-Chieh Chang, Tsun Yu Chang
  • Publication number: 20190057895
    Abstract: A manufacturing method of an interconnect structure including the following steps is provided. A dielectric layer is formed on a silicon layer, wherein an opening exposing the silicon layer is in the dielectric layer. A metal layer is formed on the surface of the opening. A stress adjustment layer is formed on the metal layer. A thermal process is performed to react the metal layer with the silicon layer to form a metal silicide layer on the silicon layer. The stress adjustment layer is removed after the thermal process is performed. A barrier layer is formed on the surface of the opening.
    Type: Application
    Filed: September 21, 2017
    Publication date: February 21, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Li-Han Chen, Chun-Chieh Chiu, Wei-Chuan Tsai, Yen-Tsai Yi
  • Publication number: 20190056563
    Abstract: A lens structure includes a lens barrel, a first lens and an opaque layer. The lens barrel has an axially-extended accommodation space. The first lens includes a surface and is disposed in the accommodation space, wherein the surface includes a light penetrating zone, and the light penetrating zone includes an optical axis passing through a center of the first lens. The opaque layer is formed on the surface and disposed between the light penetrating zone and the lens barrel. The lens structure satisfies: 0.2?R/HO?0.8, wherein R is an effective radius of the first lens, and HO is half of an outer diameter of the first lens.
    Type: Application
    Filed: May 2, 2018
    Publication date: February 21, 2019
    Inventors: Chun-Chieh Lin, Che-Hao Chuang
  • Patent number: 10211244
    Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front surface, at least one light-sensing region close to the front surface, and a first trench surrounding the light-sensing region. The first trench has an inner wall and a bottom surface. The image sensor device includes an insulating layer covering the back surface, the inner wall, and the bottom surface. A thickness of a first upper portion of the insulating layer in the first trench increases in a direction away from the front surface, and the insulating layer has a second trench partially in the first trench. The image sensor device includes a reflective structure filled in the second trench. The reflective structure has a light reflectivity ranging from about 70% to about 100%.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: February 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Fang, Ming-Chi Wu, Ji-Heng Jiang, Chi-Yuan Wen, Chien-Nan Tu, Yu-Lung Yeh, Shih-Shiung Chen, Kun-Yu Lin
  • Patent number: 10210783
    Abstract: An apparatus and a method for sensing a display panel are provided. The apparatus includes a source driving circuit and a sensing circuit. The source driving circuit is coupled to data lines to drive the pixel circuits according to a scan-line period for scanning one of the scan lines. The sensing circuit is coupled to a plurality of pixel circuits. The sensing circuit senses characteristics of the pixel circuits according to the scan-line period for scanning one of the scan lines, wherein the scan-line period comprises a display data period and a test data period. In the test data period, a corresponding pixel circuit receives test data, and the sensing circuit senses the electrical characteristic of the corresponding pixel circuit. In the display data period, the corresponding pixel circuit receives display data from a corresponding data line, and the sensing circuit does not sense the corresponding pixel circuit.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: February 19, 2019
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chun-Chieh Lin, Shang-I Liu, Hua-Gang Chang
  • Publication number: 20190050890
    Abstract: A video dotting placement analysis method is disclosed, including: converting a content of the video into a plurality of descriptor lists, wherein each descriptor list is recorded with a time sequence and a plurality of raw descriptors; providing an advertisement category (ADC) model recorded with relationships among a plurality of advertisement categories and a plurality of descriptors; performing analysis on the ADC model and the plurality of descriptor lists to generate a plurality of ADC recommendation lists, wherein the plurality of ADC recommendation lists is recorded with category relevance confidences between each advertisement category and the video content corresponded to each time sequences; calculating predicted audience response (AR) values of each advertisement category; and analyzing one or multiple time sequences as a dotting placement of the video based on the plurality of ADC recommendation lists, the plurality of predicted AR values and a dotting model.
    Type: Application
    Filed: April 2, 2018
    Publication date: February 14, 2019
    Inventors: Yun-Fu LIU, Shao-Hang HSIEH, Chien-Yu LIN, Chun-Chieh HUANG
  • Publication number: 20190046806
    Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.
    Type: Application
    Filed: October 8, 2018
    Publication date: February 14, 2019
    Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung
  • Publication number: 20190050503
    Abstract: An automated electronic component footprint setup system and a method thereof are provided in the present disclosure. The system is available to not only an external first user for configuring characteristic parameters of an electronic component for the database but also an external second user for configuring setup parameters of an electronic component footprint to be created. Then, the system is to create an electronic component footprint of a specific electronic layout system according to the characteristic parameters of the electronic component, component setup regulations and the setup parameters, all of which correspond to the electronic component footprint.
    Type: Application
    Filed: August 8, 2017
    Publication date: February 14, 2019
    Applicant: FootPrintKu Inc.
    Inventors: Cheng-Ta Lu, Yu-Siang Fan Jiang, Jiun-Huei Ho, Chun-Chieh Tsai, Yi-Ting Chen
  • Patent number: 10205159
    Abstract: An exemplary embodiment of a synthesis method includes the following acts or steps: providing LiMn2O4 material as a precursor; leaching Mn from the LiMn2O4 material using an acid to form a synthesized solution; adding carbonaceous material to the synthesized solution; adding phosphoric acid to the synthesized solution with carbonaceous material to form MnPO4 composite material; and adding Li containing compound to the MnPO4 composite material to form LiMnPO4 composite material.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: February 12, 2019
    Assignee: CHANGS ASCENDING ENTERPRISE CO., LTD.
    Inventors: Chun-Chieh Chang, Tsun Yu Chang
  • Patent number: 10206094
    Abstract: A user equipment (UE) context migration management method applied to a mobile edge platform (MEP) for managing a UE context of a mobile communication device is provided. An embodiment includes: receiving a migration completion indication of a mobile communication device; obtaining source platform information corresponding to the mobile communication device according to the migration completion indication, wherein the source platform information at least includes a location information of a source MEP; and transmitting a first request to the source MEP according to the source platform information to obtain an pointer information of the UE context of the mobile communication device from the source MEP, wherein the pointer information at least indicates a location where the UE context of the mobile communication device locates and the location information of the source MEP.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: February 12, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Kuo-Wei Wen, Chun-Chieh Wang, Jian-Hao Chen
  • Publication number: 20190043912
    Abstract: Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device comprises a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. The semiconductor device comprises a guard structure disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region.
    Type: Application
    Filed: October 1, 2018
    Publication date: February 7, 2019
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Feng-Chi Hung, Min-Feng Kao
  • Patent number: 10199269
    Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Han Chen, Yen-Tsai Yi, Chun-Chieh Chiu, Min-Chuan Tsai, Wei-Chuan Tsai, Hsin-Fu Huang
  • Publication number: 20190036013
    Abstract: A magnetoresistive random access memory (MRAM) structure and a method of forming the same are provided. The MRAM structure includes a conductive pillar over a substrate, a first MTJ spacer and a first conductive layer. The first MTJ spacer surrounds the conductive pillar. The first conductive layer surrounds the first MTJ spacer. The first magnetic tunnel junction (MTJ) spacer includes a first electrode, a second electrode and a magnetic tunnel junction (MTJ) layer. The first electrode is in contact with the conductive pillar and the substrate. The second electrode is positioned over the first electrode and in contact with the first conductive layer. The magnetic tunnel junction (MTJ) layer is positioned between the first electrode and the second electrode.
    Type: Application
    Filed: July 31, 2017
    Publication date: January 31, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh MO, Tsai-Hao HUNG, Shih-Chi KUO
  • Publication number: 20190031720
    Abstract: Modified capsid proteins containing at least a portion of hepatitis E virus (HEV) open reading frame 2 (ORF2) having one or more cysteine residues in a surface variable loop or the C-terminus of HEV ORF2, or a portion thereof, are provided. The modified capsid proteins can be used to form hepatitis E virus (HEV) virus like particles (VLPs) having cysteine functional groups exposed on the outer-surface. The exposed cysteine functional groups can be modified via their thiol reactive group. For example, a bioactive agent, such as a cell-targeting ligand, can be conjugated to the one or more cysteines for targeted delivery of chemically activated nanocapsids.
    Type: Application
    Filed: August 3, 2018
    Publication date: January 31, 2019
    Inventors: R. HOLLAND CHENG, LI XING, CHUN CHIEH CHEN, MARIE STARK
  • Publication number: 20190035694
    Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.
    Type: Application
    Filed: July 31, 2017
    Publication date: January 31, 2019
    Inventors: Shahaji B. More, Zheng-Yang Pan, Chun-Chieh Wang, Shih-Chieh Chang
  • Patent number: 10193090
    Abstract: In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: January 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Lu, Jean-Pierre Colinge, Ken-Ichi Goto, Zhiqiang Wu, Yu-Ming Lin
  • Patent number: 10192918
    Abstract: An image sensor includes a substrate having a pixel region and a periphery region. The image sensor further includes a first isolation structure formed in the pixel region; the first isolation structure including a first trench having a first depth. The image sensor further includes a second isolation structure formed in the periphery region; the second isolation structure including a second trench having a second depth. The second depth is greater than the first depth.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: January 29, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Volume Chien
  • Patent number: 10187551
    Abstract: A multifunction peripheral system includes a server and a multifunction peripheral. The server is configured to access printing information from a first electronic device, and is further configured to generate printing verification information corresponding to the printing information. The multifunction peripheral has a communication connection with the server. The multifunction peripheral is configured to access a detectable identifier, which comprises information to be verified, from a second electronic device, and the multifunction peripheral further configured to ask the server the printing information according to the detectable identifier. When the information to be verified is identical to the printing verification information, the server provides the printing information to the multifunction peripheral.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: January 22, 2019
    Assignee: Avision Inc.
    Inventor: Chun-Chieh Liao
  • Patent number: 10181684
    Abstract: A power connector has a power input port, a power output port, a signal transmission port, a controller, and a bridging circuit. The power input port is configured to receive input power. The power output port is applicable for plugging into an external device so as to provide output power to the external device. The signal transmission port is applicable for plugging into the external device to receive an indication signal. The controller is electrically connected to the signal transmission port and configured to adjust a control signal based on the indication signal. The bridging circuit is respectively electrically connected to the power input port, the power output port, and the controller, and controlled by the control signal to selectively transfer part of the input power to the power output port as the output power.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: January 15, 2019
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventors: Hsiang-Chun Hu, Chun-Chieh Lu
  • Patent number: 10181342
    Abstract: A method for improving a program speed of a memory includes acquiring a program level of the memory, comparing the program level of the memory with a valid level and a target level for generating a comparison result, and entering a first loop and/or a second loop for setting a program voltage of the memory according to the comparison result.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: January 15, 2019
    Assignee: eMemory Technology Inc.
    Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching, Chun-Chieh Chao