Abstract: A method of packaging a fiber optic module comprising steps of: connecting a fiber optic connector with a mounting holder; fixing the mounting holder on a circuit board; mounting a photoelectric array element on the circuit board; and connecting a lens element with the mounting holder. The mounting holder includes a body, an accommodation trench, multiple orifices, two protrusions, and two first fixing holes. The fiber optic connector includes multiple optical fiber cables, and glue is fed into the accommodation trench. The photoelectric array element is mounted on the circuit board. The lens element includes two slots and two positioning columns, wherein the two slots respectively accommodate the two protrusions of the mounting holder, and the two positioning columns insert into the two first fixing holes of the mounting holder respectively.

Abstract: A display device comprised of OLEDs and micro LEDs which allows for blue light degradation of the OLEDs includes a first substrate and a second substrate in a double-decked configuration. First light emitting elements are located and spaced on the first substrate and second light emitting elements are located and spaced on the second substrate, the light emitting elements on the lower deck being staggered so as not to be hidden by the light emitting elements on the upper deck. The upper deck has openings (or is transparent) therein to allow egress of light from the light emitting elements of the lower deck. The display device provides a solution for uneven display cause by degradation of pixels.

Abstract: Apparatuses and methods for performing a post-CMP cleaning are provided. The apparatus includes a chamber configured to receive a wafer in need of having CMP residue removed. The apparatus also includes a spray unit configured to apply a first cleaning solution to at least one surface of the wafer. The apparatus further includes a brush cleaner configured to scrub the at least one surface of the wafer. In addition, the apparatus includes at least one inner tank disposed in the chamber for storing a second cleaning solution that is used to clean the brush cleaner.

Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front surface, at least one light-sensing region close to the front surface, and a first trench surrounding the light-sensing region. The first trench has an inner wall and a bottom surface. The image sensor device includes an insulating layer covering the back surface, the inner wall, and the bottom surface. A thickness of a first upper portion of the insulating layer in the first trench increases in a direction away from the front surface, and the insulating layer has a second trench partially in the first trench. The image sensor device includes a reflective structure filled in the second trench. The reflective structure has a light reflectivity ranging from about 70% to about 100%.

Abstract: A method for identifying extension messages of a video includes: providing a video; converting content of the video into a content list including a plurality of descriptor lists, each descriptor list recording a time interval and raw descriptors for describing a feature presented in the video at the time interval; providing a descriptor semantic model (DSM) including a plurality of node descriptors and a plurality of directed edges wherein each node descriptor corresponds to a predetermined feature, and the directed edges define relation strengths among the node descriptors; importing the raw descriptors of the descriptor list into the DSM to update the raw descriptors as refined descriptors and to obtain one or more inferred descriptors; and updating the descriptor lists based on the refined descriptors and the inferred descriptors. An identification system and storage media thereof are also provided.

Abstract: A semiconductor device including an active layer made of III-V group semiconductors, a source electrode and a drain electrode disposed on the active layer, a gate electrode disposed on or above the active layer and between the source electrode and the drain electrode, an interlayer dielectric covering the source electrode, the drain electrode, and the gate electrode and having a plurality of inter-gate via holes. The semiconductor device further includes an inter-source layer, an inter-drain layer, and an inter-gate layer disposed on the interlayer dielectric. The semiconductor device further includes an inter-gate plug filled in the inter-gate via hole and electrically connected to the gate electrode and the inter-gate layer, and a gate field plate being separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer.

Abstract: Apparatuses and methods for performing a post-CMP cleaning are provided. The apparatus includes a chamber configured to receive a wafer in need of having CMP residue removed. The apparatus also includes a spray unit configured to apply a first cleaning solution to at least one surface of the wafer. The apparatus further includes a brush cleaner configured to scrub the at least one surface of the wafer. In addition, the apparatus includes at least one inner tank disposed in the chamber for storing a second cleaning solution that is used to clean the brush cleaner.

Abstract: A method for performing time and cell de-interleaving on an interleaved signal including a plurality of cells is provided. The method includes: providing a first memory for storing the cells, the first memory written and read each time in a unit of one cell group, the cell group including K cells, where K is a positive integer greater than 1; providing a second memory for storing the cells read from the first memory; reading the cells from the first memory, and writing the cells to the second memory according to a writing rule of a plurality of permutation rules, K consecutive cells written to the second memory being from the same cell group; and reading the cells from the second memory according to a reading rule of the permutation rules, to cause the cells read from the second memory to be complete with time de-interleaving and cell de-interleaving.

Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain structure near the gate structure. The source/drain structure has an inner portion and an outer portion surrounding an entirety of the inner portion. The inner portion has a greater average dopant concentration than that of the outer portion.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.

Abstract: An electronic device and a hinge assembly thereof are provided. The hinge assembly includes a first and a second fixed block, a first and a second polyline rod, a damper rod and a fastener. The first fixed block has a first and a second end, the second fixed block has a third and a fourth end, and the first polyline rod has a fifth and a sixth end, wherein the fifth end is connected to the second end, and the sixth end is connected to the fourth end. The second polyline rod has a seventh connected to the fourth end, and an eighth end, connected to the second end and the sixth end. The damper rod is slidably disposed on the first fixed block, the fastener is fixed to the first fixed block, and a distal end of the damper rod is fastened into the fastener.

Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.

Abstract: An apparatus and a method for sensing a display panel are provided. The apparatus includes a source driving circuit and a sensing circuit. The source driving circuit is coupled to data lines to drive the pixel circuits according to a scan-line period for scanning one of the scan lines. The sensing circuit is coupled to a plurality of pixel circuits. The sensing circuit senses characteristics of the pixel circuits according to the scan-line period for scanning one of the scan lines, wherein the scan-line period comprises a display data period and a test data period. In the test data period, a corresponding pixel circuit receives test data, and the sensing circuit senses the electrical characteristic of the corresponding pixel circuit. In the display data period, the corresponding pixel circuit receives display data from a corresponding data line, and the sensing circuit does not sense the corresponding pixel circuit.

Abstract: In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer.

Abstract: The present invention provides a method for forming a contact structure, the method includes proving a substrate. An oxygen-containing dielectric layer is formed on the substrate. Next, a non-oxygen layer is formed on the oxygen-containing dielectric layer and a contact hole is then formed in the oxygen-containing dielectric layer. A metal layer is then formed in the contact hole and on the non-oxygen layer, with the non-oxygen layer disposed between the oxygen-containing dielectric layer and the metal layer. An anneal process is then performed to the metal layer, and a conductive layer is filled in the contact hole.

Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.

Abstract: A semiconductor device includes a substrate, light-sensing devices and a bonding layer. The substrate overlies the carrier, and has a first surface and a second surface opposite to the first surface. The substrate includes recesses in the second surface, and surfaces of each of the recesses are wet etched surfaces. The light-sensing devices are disposed on the first surface of the substrate. The bonding layer is disposed between the substrate and the carrier.

Abstract: Provided is a capacitor structure including a substrate, a cup-shaped lower electrode, a top supporting layer, a capacitor dielectric layer, and an upper electrode. The cup-shaped lower electrode is located on the substrate. The top supporting layer surrounds the upper portion of the cup-shaped lower electrode. The top supporting layer includes a high-k material. Surfaces of the cup-shaped lower electrode and the top supporting layer are covered by the capacitor dielectric layer. A surface of the capacitor dielectric layer is covered by the upper electrode.

Abstract: An electronic device and a hinge assembly thereof are provided. The hinge assembly includes a first and a second fixed block, a first and a second connecting rod, a damper rod and a fastener. The first fixed block has a first and a second end, the second fixed block has a third and a fourth end, and the first connecting rod has a fifth and a sixth end, wherein the fifth end is connected to the second end, and the sixth end is connected to the fourth end. The second connecting rod has a seventh connected to the fourth end, and an eighth end, connected to the second end and the sixth end. The damper rod is slidably disposed on the first fixed block, the fastener is fixed to the first fixed block, and a distal end of the damper rod is fastened into the fastener.

Abstract: A semiconductor structure includes a first-type doped semiconductor layer, a light emitting layer, a second-type doped semiconductor layer comprising AlxInyGa1-x-yN layers, at least one GaN based layer, and an ohmic contact layer. The light emitting layer is disposed on the first-type doped semiconductor layer, and the second-type doped semiconductor layer is disposed on the light emitting layer. The AlxInyGa1-x-yN layers stacked on the light emitting layer, where 0<x<1, 0?y<1, and 0<x+y<1, and the GaN based layer interposed between two of the AlxInyGa1-x-yN layers, and the ohmic contact layer is disposed on the AlxInyGa1-x-yN layers.