Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180344030
    Abstract: A vibration isolation cabinet assembly includes a single cabinet or a cabinet set installed on a vibration isolation module. The cabinet set is composed of multiple cabinets and located on a vibration isolation module. The vibration isolation module is composed of multiple vibration isolation devices. When earthquake happens, the transverse waves of the earthquake do not reach the cabinet and the cabinet sets because of the vibration isolation module and the vibration isolation devices.
    Type: Application
    Filed: June 5, 2017
    Publication date: December 6, 2018
    Inventors: Chun-Chieh Yao, Cheng-Yi Ke
  • Publication number: 20180350675
    Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.
    Type: Application
    Filed: July 31, 2018
    Publication date: December 6, 2018
    Inventors: Chien-Hao Chung, Chang-Sheng Lin, Kuo-Feng Huang, Li-Chieh Wu, Chun-Chieh Lin
  • Publication number: 20180350898
    Abstract: A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers.
    Type: Application
    Filed: August 10, 2018
    Publication date: December 6, 2018
    Inventors: Chewn-Pu Jou, Chih-Hsin Ko, Po-Wen Chiu, Chao-Ching Cheng, Chun-Chieh Lu, Chi-Feng Huang, Huan-Neng Chen, Fu-Lung Hsueh, Clement Hsingjen Wann
  • Publication number: 20180345329
    Abstract: A piping system is provided, connecting a plurality of scrubbers which are disposed on a supporting structure, including a collecting pipe and a drain pipe. The collecting pipe has a main body and a plurality of protrusions, wherein the main body has an outer surface and a first central axis. The protrusions are protruding from the outer surface, and the first central axis is perpendicular to the supporting structure. The collecting pipe communicates with the scrubbers via the protrusions. The drain pipe is disposed under the supporting structure and has a second central axis, wherein the collecting pipe is extended through the supporting structure and connects to the drain pipe, and the first central axis is perpendicular to the second central axis.
    Type: Application
    Filed: November 27, 2017
    Publication date: December 6, 2018
    Inventors: Peng-Tan LU, Chun-Chieh CHOU, Chun-Pin HUANG, Liang-Chih CHANG, Chih-Nan LIN
  • Patent number: 10147845
    Abstract: A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure mainly includes a stress control layer disposed between a light emitting layer and a p-type carrier blocking layer. The p-type carrier blocking layer is made from AlxGa1-xN (0<x<1) while the stress control layer is made from AlxInyGa1-x-yN (0<x<1, 0<y<1, 0<x+y<1). The light emitting layer has a multiple quantum well structure formed by a plurality of well layers and barrier layers stacked alternately. There is one well layer disposed between the two barrier layers. Thereby the stress control layer not only improves crystal quality degradation caused by lattice mismatch between the p-type carrier blocking layer and the light emitting layer but also reduces effects of compressive stress on the well layer caused by material differences.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: December 4, 2018
    Assignee: Genesis Photonics Inc.
    Inventors: Chi-Feng Huang, Ching-Liang Lin, Shen-Jie Wang, Jyun-De Wu, Yu-Chu Li, Chun-Chieh Lee
  • Publication number: 20180340041
    Abstract: A method for producing a polyester includes: a) subjecting a mixture which includes a major amount of a first monomer and a minor amount of a second monomer to a pre-polymerization reaction at a first temperature for a period of reaction time such that a prepolymer is formed while a glycol compound is continuously removed by distillation; and b) subjecting the prepolymer to a polymerization reaction at a second temperature higher than the first temperature to obtain the polyester.
    Type: Application
    Filed: July 19, 2017
    Publication date: November 29, 2018
    Applicant: Far Eastern New Century Corporation
    Inventors: Chun-Chieh CHIEN, Chih-Chien Lin
  • Publication number: 20180341663
    Abstract: A method of searching an image file includes: utilizing a login module to log in a user account; utilizing an input module to store an image file at a predetermined location; utilizing an information capturing module to capture at least one image information of the image file stored at the predetermined location; utilizing an index building module to build at least one index tag corresponding to the image file according to the at least one image information captured by the information capturing module; utilizing a searching module to receive at least one searching condition so as to search the at least one index tag according to the at least one searching condition; and utilizing a display module to display a searching result corresponding to the image file when the at least one index tag matches with the at least one searching condition.
    Type: Application
    Filed: March 19, 2018
    Publication date: November 29, 2018
    Inventors: Chun-Chieh Liao, Chun-Ping Huang, Hung-Jen Lin
  • Publication number: 20180343359
    Abstract: A controlled device, a control device, a control system using the same and a control method using the same are provided. The controlled device is configured for receiving a trigger event, and outputting a trigger signal in response to the trigger event. The control device is configured for receiving the trigger signal from the controlled device, and loading an application program corresponding to the trigger event in response to the trigger signal.
    Type: Application
    Filed: April 23, 2018
    Publication date: November 29, 2018
    Inventor: Chun-Chieh LIAO
  • Patent number: 10140209
    Abstract: A time de-interleaving circuit applied to a communication system to de-interleave an interleaved signal is provided. The interleaved signal includes a plurality of cells. The time de-interleaving circuit includes a memory module and a buffering memory module. The memory module stores the cells, which are in a unit of a plurality of cells to form a plurality of cell groups. The memory module is accessed in a unit of one cell group. The buffering memory module buffers a part of the cells from the memory module to arrange an output sequence of the cells.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: November 27, 2018
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventor: Chun-Chieh Wang
  • Publication number: 20180338055
    Abstract: An image capturing method and an image capturing device using the same are provided. The image capturing method includes the following steps. Firstly, the image capturing device receives a paper sheet having a plurality of regions. Then, the image capturing device provides a user interface. Then, in response to an operation of a user to the user interface, an arrangement regulation of the regions is set. Then, the image capturing device captures a plurality of region images of the regions of the paper sheet. Then, the image capturing device arranges the region images according to the arrangement regulation.
    Type: Application
    Filed: November 27, 2017
    Publication date: November 22, 2018
    Inventor: Chun-Chieh Liao
  • Publication number: 20180337056
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Rueijer Lin, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su
  • Publication number: 20180329483
    Abstract: A 3D positioning system and method, adapted for object tracking and positioning of virtual reality is provided. The method comprises: tracking a characteristic of at least a light-emitting component at a controller; calculating relative displacement information between each of the controller and a headset display device according to the characteristic; detecting first displacement information of the headset display device and second displacement information of each of the controller; transmitting the relative displacement information, the first displacement information, and the second displacement information to the host; and adjusting a corresponding virtual image of the virtual reality according to the relative displacement information, the first displacement information, and the second displacement information and transmitting the adjusted virtual image to the headset display device to display via the host.
    Type: Application
    Filed: May 2, 2018
    Publication date: November 15, 2018
    Inventors: Ping-Fu HSIEH, Chih-Lung LIN, Chun-Chieh CHUANG, Hui-Chun CHUNG, Wei-Chung HUNG, Pei-Lun HAN, Tse-Wei LIN
  • Patent number: 10126879
    Abstract: A testing method of a touch device and a system thereof are provided. The testing method includes following steps. A test sensing information generated by the touch device is received, and the test sensing information is physical characteristic information provided by sensors of the touch device. A test gesture signal and a test keypad signal generated by the touch device are received, the test gesture signal includes gesture coordinates provided by touch device, and the test keypad signal includes a keypad key triggering signal generated by the touch device. According to a preset table, in order to generate a test result, whether the test sensing information, the test gesture signal, and the test keypad signal match data of the preset table or not is determined, and whether the touch device works properly is determined according to the test result.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: November 13, 2018
    Assignee: Wistron Corporation
    Inventors: Shih-Wen Chen, Chun-Chieh Li, Ya-Ping Lin
  • Patent number: 10129991
    Abstract: A foldable electronic device and a linking assembly are provided. The foldable electronic device includes a host and a foldable display attached to the host. The host has a first portion, a second portion and a linking assembly connected therebetween. The linking assembly includes N+1 blocks (wherein N is an integer greater than or equal to 2) and a plurality of linking sets. Each block has a body and a pair of fitting portions disposed at two opposite sides of the body in a sliding mirror symmetry manner along a first direction, and the fitting portion of the Nth block is fitted with the fitting portion of the N+1 block. Each linking set has two links, and two ends of the two links overlapping each other lean against the Nth block and can move relative to the Nth block. Other two ends of the two links without overlapping each other are respectively fixed to the N?1th and N+1th blocks. When the link assembly is bent, a virtual center of any two adjacent blocks locates within a scope of the foldable display.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: November 13, 2018
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Chia-Chi Lin, Jui-Min Huang, Chun-Chieh Chen, Ching-Tai Chang, Cheng-Ya Chi
  • Patent number: 10121243
    Abstract: Methods are herein provided for decision support in diagnosis of a disease in a subject, and for extracting features from a multi-slice data set. Systems for computer-aided diagnosis are provided. The systems take as input a plurality of medical data and produces as output a diagnosis based upon this data. The inputs may consist of a combination of image data and clinical data. Diagnosis is performed through feature selection and the use of one or more classifier algorithms.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: November 6, 2018
    Assignee: Koninklijke Philips N.V.
    Inventors: Lilla Boroczky, Lalitha Agnihotri, Luyin Zhao, Michael Chun-Chieh Lee, Charles Andrew Powell, Alain C. Borczuk, Steven Kawut
  • Publication number: 20180314470
    Abstract: An output method and an output device include steps below. A first electronic device sends a file to a server and generates a piece of verification information corresponding to the file. A second electronic device receives the piece of verification information. An output device reads the piece of verification information, and obtains the file from the server according to the piece of verification information. The output device receives a first verification code via a user interface, determines whether the first verification code matches the piece of verification information, and outputs the paper document of the file when the first verification code matches the piece of verification information. The output device sends a second verification code, generated according to encode data of the file, to the second electronic device for a further verification and deletes the file after the output device output the paper document of the file.
    Type: Application
    Filed: June 20, 2018
    Publication date: November 1, 2018
    Applicant: AVISION INC.
    Inventor: Chun-Chieh LIAO
  • Publication number: 20180315462
    Abstract: A method for improving a program speed of a memory includes acquiring a program level of the memory, comparing the program level of the memory with a valid level and a target level for generating a comparison result, and entering a first loop and/or a second loop for setting a program voltage of the memory according to the comparison result.
    Type: Application
    Filed: November 3, 2017
    Publication date: November 1, 2018
    Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching, Chun-Chieh Chao
  • Publication number: 20180307134
    Abstract: The present disclosure relates to a method of using an equipment for manufacturing or using a mask or a display substrate; and the method includes: providing a master plate; setting, on the master plate, a plurality of measuring points corresponding to positions of the mask or the display substrate where a pixel position accuracy measurement is to be implemented, according to the mask or the display substrate to be measured; and placing the master plate in a coordinate system of the equipment, and measuring error values between the equipment and the master plate at the measuring points.
    Type: Application
    Filed: March 9, 2017
    Publication date: October 25, 2018
    Inventors: Zhiming Lin, Zhen Wang, Jian Zhang, Chun Chieh Huang
  • Patent number: 10109523
    Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hao Chung, Chang-Sheng Lin, Kuo-Feng Huang, Li-Chieh Wu, Chun-Chieh Lin
  • Publication number: 20180294357
    Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain structure near the gate structure. The source/drain structure has an inner portion and an outer portion surrounding an entirety of the inner portion. The inner portion has a greater average dopant concentration than that of the outer portion.
    Type: Application
    Filed: June 11, 2018
    Publication date: October 11, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. MORE, Zheng-Yang PAN, Chun-Chieh WANG, Cheng-Han LEE, Shih-Chieh CHANG