Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Diode device and method for manufacturing the same
    Patent number: 9640672
    Abstract: A diode device including a III-N compound layer is provided. The III-N compound layer has a channel region therein. A cathode region is located on the III-N compound layer. A first anode region is located on the III-N compound layer and extends into the III-N compound layer. The bottom of the first anode region is under the channel region. A second anode region is located on the III-N compound layer between the cathode region and the first anode region, and extends into the III-N compound material layer. The second anode region includes a high-energy barrier region. The high-energy barrier region adjoins a sidewall of the first anode region. A method for manufacturing a diode device is also provided.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: May 2, 2017
    Assignees: National Central University, Delta Electronics, Inc.
    Inventors: Jen-Inn Chyi, Bo-Shiang Wang, Chun-Chieh Yang, Geng-Yen Lee
  • Axially symmetric LED light bulb
    Patent number: 9638390
    Abstract: An axially symmetric LED light bulb includes a lamp shade, a substrate and a connecting seat. The substrate installed on the connecting seat includes plural LED light sources. The lamp shade has an edge connected to the connecting seat, and the substrate is covered inside the lamp shade. The lamp shade has an unequal thickness with a thicker top and thinner sides. The axially symmetric LED light bulb provides excellent light uniformity and wide-angle illumination.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: May 2, 2017
    Assignee: Unity Opto Technology Co., Ltd.
    Inventors: Chih-Hsien Wu, Sen-Yuh Tsai, Chun-Chieh Huang, Yu-Chang Chen
  • SEMICONDUCTOR PROCESS AND SEMICONDUCTOR DEVICE
    Publication number: 20170117379
    Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.
    Type: Application
    Filed: October 27, 2015
    Publication date: April 27, 2017
    Inventors: Pin-Hong Chen, Kuo-Chih Lai, Chia-Chang Hsu, Chun-Chieh Chiu, Li-Han Chen, Min-Chuan Tsai, Kuo-Chin Hung, Wei-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu
  • Chemically Activated Nanocapsid Functionalized for Cancer Targeting
    Publication number: 20170107261
    Abstract: Modified capsid proteins containing at least a portion of hepatitis E virus (HEV) open reading frame 2 (ORF2) having one or more cysteine residues in a surface variable loop or the C-terminus of HEV ORF2, or a portion thereof, are provided. The modified capsid proteins can be used to form hepatitis E virus (HEV) virus like particles (VLPs) having cysteine functional groups exposed on the outer-surface. The exposed cysteine functional groups can be modified via their thiol reactive group. For example, a bioactive agent, such as a cell-targeting ligand, can be conjugated to the one or more cysteines for targeted delivery of chemically activated nanocapsids.
    Type: Application
    Filed: May 18, 2015
    Publication date: April 20, 2017
    Inventors: R. Holland Cheng, Li Xing, Chun Chieh Chen, Marie Stark
  • Method and apparatus for low resistance image sensor contact
    Patent number: 9627430
    Abstract: A method and apparatus for a low resistance image sensor contact, the apparatus comprising a photosensor disposed in a substrate, a first ground well disposed in a first region of the substrate, the first ground well having a resistance lower than the substrate, and a ground line disposed in a region adjacent to the first ground well. The first ground well is configured to provide a low resistance path to the ground line from the substrate for excess free carriers in the first region of the substrate. The apparatus may optionally comprise a second ground well having a lower resistance than the first ground well and disposed between the first ground well and the ground line, and may further optionally comprise a third ground well having a lower resistance than the second ground well and disposed between the second ground well and the ground line.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chun-Chieh Chuang, Shuang-Ji Tsai, Jeng-Shyan Lin
  • METHOD FOR MANUFACTURING NEGATIVE PLATE OF SECONDARY BATTERY
    Publication number: 20170104213
    Abstract: The present invention provides a method for manufacturing a negative plate of a secondary battery, which includes the following steps: providing multiple sheets of functional graphene; compressing the functional graphene to form a graphene target; providing copper foil, and forming a microstructure on a surface of the copper foil, so as to strengthen attachment between a graphene layer and the copper foil; depositing the graphene target on the microstructure of the surface of the copper foil, to form the graphene layer; and repairing the graphene layer by using an excimer laser. The foregoing manufacturing method can greatly prolong a cycle life of the whole graphene cathode, and increase a reversible capacitance of a battery.
    Type: Application
    Filed: December 15, 2015
    Publication date: April 13, 2017
    Inventors: Chia-Hung HUANG, Sung-Mao CHIU, Chi-Wen CHU, Yin CHUANG, Chun-Chieh WANG, Chia-Min WEI
  • Self-excited power conversion circuit for secondary side control output power
    Patent number: 9621060
    Abstract: A self-excited power conversion circuit for secondary side control output power includes a comparator unit and a transistor installed directly in a secondary side output module, and the comparator unit is electrically coupled to at least one load, and the transistor is electrically coupled between to a conversion module of the circuit and the load. The comparator unit is provided for adjusting the duty cycle of the transistor after detecting the amount of energy outputted from the conversion module to the load from, so as to adjust the amount of energy actually received by the load to achieve a constant power effect.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: April 11, 2017
    Assignee: Anwell Semiconductor Corp.
    Inventors: Cheng-Po Hsiao, Chung-Hsin Huang, Ke-Horng Chen, Chun-Chieh Kuo, Shih-Ping Tu, Shao-Wei Chiu
  • Structure and Method for 3D Image Sensor
    Publication number: 20170098679
    Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.
    Type: Application
    Filed: December 19, 2016
    Publication date: April 6, 2017
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Feng-Chi Hung, Shuang-Ji Tsai, Jeng-Shyan Lin, Shu-Ting Tsai, Wen-I Hsu
  • Backside structure and methods for BSI image sensors
    Patent number: 9613996
    Abstract: A back side image sensor and method of manufacture are provided. In an embodiment a bottom anti-reflective coating is formed over a substrate, and a metal shield layer is formed over the bottom anti-reflective coating. The metal shield layer is patterned to form a grid pattern over a sensor array region of the substrate, and a first dielectric layer and a second dielectric layer are formed to at least partially fill in openings within the grid pattern.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang, Keng-Yu Chou, Shuang-Ji Tsai, Min-Feng Kao
  • Post-CMP Cleaning and Apparatus
    Publication number: 20170092481
    Abstract: A method includes performing a first post Chemical Mechanical Polish (CMP) cleaning on a wafer using a first brush. The first brush rotates to clean the wafer. The method further includes performing a second post-CMP cleaning on the wafer using a second brush. The second brush rotates to clean the wafer. The first post-CMP cleaning and the second post-CMP cleaning are performed simultaneously.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 30, 2017
    Inventors: Fu-Ming Huang, Liang-Guang Chen, Ting-Kui Chang, Chun-Chieh Lin
  • SEMICONDUCTOR DEVICE
    Publication number: 20170092642
    Abstract: A semiconductor device includes an element layer, plural source electrodes, plural drain electrodes, plural gate electrodes, a source bus bar, a drain bus bar, a first gate bus bar, and a second gate bus bar. The source electrodes, the drain electrodes, and the gate electrodes are disposed on the element layer and extend along a first direction. The gate electrodes are respectively disposed between the source and drain electrodes. The source and drain bus bars and the first and second gate bus bars extend along a second direction interlaced with the first direction. The source bus bar and the drain bus bar are electrically connected to the source electrodes and the drain electrodes, respectively. The first and second gate bus bars are connected to the gate electrodes. The first bus bar is disposed at one end of the source electrodes. The source electrode crosses the second gate bus bar.
    Type: Application
    Filed: March 31, 2016
    Publication date: March 30, 2017
    Inventors: Li-Fan LIN, Chun-Chieh YANG
  • ELECTRICAL CONNECTOR WITH EXCELLENT WATERPROOF FUNCTION
    Publication number: 20170093081
    Abstract: An electrical connector has a mating cavity opening forwardly. The electrical connector has a main body, a terminal module and a sealing member. The terminal module has an insulator and a plurality of conductive terminals received therein. The conductive terminals have contacting portions exposed into the mating cavity and connecting legs. The terminal module is received in the main body. The sealing member is filled in a gap between the terminal module and main body to seal the gap.
    Type: Application
    Filed: September 29, 2016
    Publication date: March 30, 2017
    Inventors: CHUN-CHIEH YANG, ZHI-HUI ZHU, QIN-XIN CAO
  • Display apparatus and pixel driving method with current compensation function
    Patent number: 9606645
    Abstract: A display apparatus is provided. The display device includes pixels, a data line, a first current compensation unit, a second current compensation unit, and a control unit. The first current compensation unit is configured for providing a first current to pixels through the data line. The first current is configured for compensating a leakage current that flows out of the data line. The second current compensation unit is configured for sinking a second current from pixels through the data line. The second current is configured for compensating the leakage current that flows into the data line. The control unit is configured for controlling the first current compensation unit to provide the first current or controlling the second current compensation unit to sink the second current according to a voltage of the data line.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: March 28, 2017
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chun-Chieh Lin, Hua-Gang Chang, Chih-Cheng Chen
  • SEMICONDUCTOR DEVICE HAVING INTERCONNECT LAYER THAT INCLUDES DIELECTRIC SEGMENTS INTERLEAVED WITH METAL COMPONENTS
    Publication number: 20170084485
    Abstract: An interconnect layer is disposed over a substrate. The interconnect layer includes a plurality of dielectric segments interleaved with a plurality of metal components. A plurality of vias is disposed below, and electrically coupled to, a first group of the metal components. A plurality of dielectric components is disposed underneath a second group of the metal components. The dielectric components interleave with the vias. A conductive liner is disposed below a bottom surface and on sidewalk of the vias. A dielectric barrier layer is disposed below a bottom surface and on sidewalls of the dielectric segments. The dielectric barrier layer and the dielectric segments have different material compositions.
    Type: Application
    Filed: December 6, 2016
    Publication date: March 23, 2017
    Inventors: Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai, Syun-Ming Jang
  • Semiconductor device structure and method for forming the same
    Patent number: 9601430
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a dielectric layer positioned on the semiconductor substrate. The dielectric layer has a first recess. The semiconductor device structure includes a conductive structure filling the first recess. The conductive structure includes a first conductive layer and a second conductive layer. The first conductive layer is positioned over an inner wall and a bottom of the first recess. The first conductive layer has a second recess in the first recess. The second conductive layer fills the second recess. The first conductive layer and the second conductive layer include cobalt. The second conductive layer further includes at least one of sulfur, chlorine, boron, phosphorus, or nitrogen.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: March 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Rueijer Lin, Chen-Yuan Kao, Chun-Chieh Lin, Huang-Yi Huang
  • CHANGING SCREEN BRIGHTNESS OF A COMPUTING DEVICE
    Publication number: 20170079118
    Abstract: Examples relate to changing screen brightness of a computing device. One example enables determination of whether the computing device is being used for one of a set of predetermined application types. The screen brightness of the computing device may be changed based on a set of first brightness values associated with the first predetermined application type responsive to the computing device being used for a first predetermined application type and based on a set of second brightness values associated with the second predetermined application type responsive to the computing device being used for a second predetermined application type.
    Type: Application
    Filed: May 28, 2014
    Publication date: March 16, 2017
    Inventor: CHUN-CHIEH CHEN
  • Flash memory controller
    Patent number: 9588709
    Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: March 7, 2017
    Assignee: Silicon Motion Inc.
    Inventors: Tsung-Chieh Yang, Chun-Chieh Kuo, Ching-Hui Lin, Yang-Chih Shen
  • METHOD AND SYSTEM FOR COMPUTER-AIDED PATIENT STRATIFICATION BASED ON CASE DIFFICULTY
    Publication number: 20170061087
    Abstract: When evaluating patient cases to determine complexity thereof, a computer-aided stratification technique is applied to analyze historical patient case diagnoses and correctness thereof in order to calculate a stratification score (20) for each of a plurality of abnormality types and/or anatomical locations. When a new patient case is received, the computer-aided stratification technique is applied to evaluate the patient case in view of historical data and assign a stratification score thereto. A ranked list (21) of current patient cases can be generated according to stratification scores, and physician workload can be adjusted as a function thereof so that workload is balanced across physicians and/or according to physician experience level.
    Type: Application
    Filed: April 16, 2015
    Publication date: March 2, 2017
    Inventors: LILLA BOROCZKY, MICHAEL CHUN-CHIEH LEE
  • MEMS MICROPHONE PACKAGE STRUCTURE HAVING A NON-PLANAR SUBSTRATE
    Publication number: 20170064458
    Abstract: A MEMS microphone package structure having a non-planar substrate is provided. It includes a non-planar substrate, a lid and a transducer. The non-planar substrate includes a bearing base and a peripheral wall connecting to the bearing base. The lid is covered and connected to the non-planar substrate to form a cavity, and at least one solder pad is disposed on an outer surface of the lid or the non-planar substrate. The transducer is disposed in the cavity. A sound hole is provided to correspond to the transducer, and the sound hole is disposed at the non-planar substrate or the lid.
    Type: Application
    Filed: August 31, 2015
    Publication date: March 2, 2017
    Inventors: Jen-Yi Chen, Chao-Sen Chang, Chun-Chieh Wang, Yong-Shiang Chang
  • Docking station
    Patent number: D784343
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: April 18, 2017
    Assignee: Acer Incorporated
    Inventors: Chu-Yu Chen, Ming-Haw Wang, Ting-Wei Yuan, Shang-Chuan Lin, Chun-Chieh Chiu