Abstract: An image identifying method for offline and online synchronous operation is disclosed. When the mobile device focuses on an recognition target, images frames of an recognition target are retrieved and sent to an recognition server. The mobile device executes an offline recognition operation, and synchronously an recognition server executes an online recognition operation. A plurality of the matching data is saved in the mobile device, and a plurality of recognition data is saved in an recognition server, wherein the recognition data larger than the matching data. When the mobile device firstly generates the recognition result, the recognition result is displayed for user searching reference. If the mobile device receives an recognition result from the recognition server before the mobile device completing the recognition, the recognition result replied form the recognition server is displayed on the display monitor.

Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.

Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.

Abstract: A device for robotic direct lead-through teaching includes a robot, a replacing member and a lead-through teaching member. The robot has an operation member coupled with the replacing member. The lead-through teaching member mounted replaceably at the replacing member has a force sensor. The force sensor has six-axis load information. A path teaching is executed manually upon the operation member of the robot so as to store coordinate information. In additional, a method for robotic direct lead-through teaching is also provided.

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Abstract: Methods for improving hybrid bond yield for semiconductor wafers forming 3DIC devices includes first and second wafers having dummy and main metal deposited and patterned during BEOL processing. Metal of the dummy metal pattern occupies from about 40% to about 90% of the surface area of any given dummy metal pattern region. High dummy metal surface coverage, in conjunction with utilization of slotted conductive pads, allows for improved planarization of wafer surfaces presented for hybrid bonding. Planarized wafers exhibit minimum topographic differentials corresponding to step height differences of less than about 400 ?. Planarized first and second wafers are aligned and subsequently hybrid bonded with application of heat and pressure; dielectric-to-dielectric, RDL-to-RDL. Lithography controls to realize WEE from about 0.5 mm to about 1.5 mm may be employed to promote topographic uniformity at wafer edges.

Abstract: A polisher head of a polishing apparatus includes a membrane and a first local pressure nodule and a second local pressure nodule physically contacting the membrane. The first local pressure nodule is configured to apply a first local force to the membrane and the second local pressure nodule is configured to apply a second local force to the membrane. The first local pressure nodule and the second local pressure nodule are independently controllable.

Abstract: A method for creating a report with an annotation includes receiving an input image to annotate. The method further includes comparing the input image with a set of previously annotated images. The method further includes generating a similarity metric for each of the previously annotated images based on a result of a corresponding comparison. The method further includes identifying a previously annotated image with a greatest similarity for each of a plurality of predetermined annotations. The method further includes visually displaying the identified image for each annotation along with the annotation. The method further includes receiving an input signal identifying one of the displayed images. The method further includes annotating the input image with the identified one of the displayed images. The method further includes generating, in an electronic format, a report for the input image that includes the identified annotation.

Abstract: A server, a server management system and a server management method are disclosed. The server comprises a field replaceable unit (FRU) memory and a baseboard management controller (BMC). The FRU memory stores an FRU data. The BMC receives an FRU access command from a remote management computer via an intelligent platform management interface (IPMI). The FRU access command comprises an FRU identification (ID). The BMC determines whether the FRU ID belongs to the FRU memory. If the FRU ID does not belong to the FRU memory, the BMC accesses a custom file according to the FRU ID. The custom file is different from the FRU data.

Abstract: This invention relates to a method and device for case-based decision support. It proposes that a case-based decision support system is trained on inputs from several radiologists in order to have a “baseline” system, and then the system provides an option to a radiologist to refine the baseline system based on his/her inputs which either refine weights of features for similarity distance computation directly or provide new similarity ground truth clusters. By enabling modifying the similarity distance computation based on user inputs, this invention adapts similarity ground truth to different users with different experience and/or different opinions.

Abstract: A semiconductor structure includes a first-type doped semiconductor layer, a light emitting layer, a second-type doped semiconductor layer comprising AlxInyGal-x-yN layers, at least one GaN based layer, and an ohmic contact layer. The light emitting layer is disposed on the first-type doped semiconductor layer, and the second-type doped semiconductor layer is disposed on the light emitting layer. The AlxInyGal-x-yN layers stacked on the light emitting layer, where 0<x<1, 0?y<1, and 0<x+y<1, and the GaN based layer interposed between two of the AlxInyGal-x-yN layers, and the ohmic contact layer is disposed on the AlxInyGal-x-yN layers.

Abstract: The present invention features a compound of formula I: or a pharmaceutically acceptable salt thereof, where R1, R2, R3, W, X, Y, Z, n, o, p, and q are defined herein, for the treatment of CFTR mediated diseases, such as cystic fibrosis. The present invention also features pharmaceutical compositions, method of treating, and kits thereof.

Abstract: A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure mainly includes a stress control layer disposed between a light emitting layer and a p-type carrier blocking layer. The p-type carrier blocking layer is made from AlxGa1-xN (0<x<1) while the stress control layer is made from AlxInyGa1-x-yN (0<x<1, 0<y<1, 0<x+y<1). The light emitting layer has a multiple quantum well structure formed by a plurality of well layers and barrier layers stacked alternately. There is one well layer disposed between the two barrier layers. Thereby the stress control layer not only improves crystal quality degradation caused by lattice mismatch between the p-type carrier blocking layer and the light emitting layer but also reduces effects of compressive stress on the well layer caused by material differences.

Abstract: In some embodiments, the present disclosure relates to a multi-dimensional integrated chip having a redistribution structure vertically extending between integrated chip die at a location laterally offset from a bond pad. The integrated chip structure has a first die and a second die. The first die has a first plurality of interconnect layers arranged within a first dielectric structure disposed on a first substrate. The second die has a second plurality of interconnect layers arranged within a second dielectric structure disposed between the first dielectric structure and a second substrate. A bond pad is disposed within a recess extending through the second substrate. A redistribution structure electrically couples the first die to the second die at a position that is laterally offset from the bond pad.

Abstract: A pixel driving method of a display panel is disclosed. The display panel includes a plurality of scan lines, data lines and pixels. Each of the pixel includes a first transistor with a first end coupled to the data line, and a gate end coupled to the scan line, a second transistor with a first end selectively coupled to a voltage source or current source, and a gate end coupled to a second end of the first transistor, and a light-emitting unit with a first end coupled to a second end of the second transistor. The method includes turning on the first transistors of the pixels; coupling the data lines and first ends of the second transistors to the current source; reading voltage levels of gate ends of the second transistors; and providing corresponding data voltages to the pixels according to voltage levels of gate ends of the second transistors.

Abstract: Embodiments of mechanisms for forming an image-sensor device are provided. The image-sensor device includes a substrate having a front surface and a back surface. The image-sensor device also includes a radiation-sensing region formed in the substrate. The radiation-sensing region is operable to detect incident radiation that enters the substrate through the back surface. The radiation-sensing region further includes an epitaxial isolation feature formed in the substrate and adjacent to the radiation-sensing region. The radiation-sensing region and the epitaxial isolation feature have different doping polarities.

Abstract: MRAM devices and methods of forming the same are provided. One of the MRAM devices includes a dielectric layer, a resistance variable memory cell and a conductive layer. The dielectric layer is over a substrate and has an opening. The resistance variable memory cell is in the opening and includes a first electrode, a second electrode and a magnetic tunnel junction layer between the first electrode and the second electrode. The conductive layer fills a remaining portion of the opening and is electrically connected to one of the first electrode and the second electrode of the resistance variable memory cell.

Abstract: An image sensor device includes a first substrate, an interconnect structure, a conductive layer, a conductive via and a second substrate. The first substrate includes a first region including a pixel array and a second region including a circuit. The interconnect structure is over the pixel array or the circuit. The interconnect structure electrically connecting the circuit to the pixel array. The conductive layer is on the interconnect structure. The conductive via passes through the second substrate and at least partially embedded in the conductive layer. The second substrate is over the conductive layer.

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.