Abstract: A method for performing time and cell de-interleaving on an interleaved signal including a plurality of cells is provided. The method includes: providing a first memory for storing the cells, the first memory written and read each time in a unit of one cell group, the cell group including K cells, where K is a positive integer greater than 1; providing a second memory for storing the cells read from the first memory; reading the cells from the first memory, and writing the cells to the second memory according to a writing rule of a plurality of permutation rules, K consecutive cells written to the second memory being from the same cell group; and reading the cells from the second memory according to a reading rule of the permutation rules, to cause the cells read from the second memory to be complete with time de-interleaving and cell de-interleaving.

Abstract: A Micro-Electro-Mechanical-System (MEMS) microphone device includes a substrate, a MEMS microphone thin film, oxide layer. The substrate has a first penetrating portion. The MEMS microphone thin film is above the substrate and covered the first penetrating portion defining a first cavity. The MEMS microphone thin film includes an elastic portion and a connection portion. The elastic portion has a plurality of first slots arranged along the edge of the elastic portion and sequentially and separately. The first slots are penetrated two surface of the elastic portion, the surface are opposite each other. The connection portion is connected to the elastic portion and contacted the substrate. The oxide layer has a second penetrating portion. The oxide layer is on the MEMS microphone thin film and contacted the connection portion. A part of the MEMS microphone thin film is exposed through the second penetrating portion.

Abstract: The present disclosure relates to a multi-dimensional integrated chip having a redistribution layer vertically extending between integrated chip die, which is laterally offset from a back-side bond pad. The multi-dimensional integrated chip has a first integrated chip die with a first plurality of metal interconnect layers disposed within a first inter-level dielectric layer arranged onto a front-side of a first semiconductor substrate. The multi-dimensional integrated chip also has a second integrated chip die with a second plurality of metal interconnect layers disposed within a second inter-level dielectric layer abutting the first ILD layer. A bond pad is disposed within a recess extending through the second semiconductor substrate. A redistribution layer vertically extends between the first plurality of metal interconnect layers and the second plurality of metal interconnect layers at a position that is laterally offset from the bond pad.

Abstract: A method for distributed interference coordination is provided. The method includes: forming a group of multiple small cells, selecting one of the small cells to be a group leader for the group, and performing time-domain interference coordination on the group by the group leader.

Abstract: A semiconductor structure is provided, which includes a semiconductor substrate, a first well region, a second well region, an active region, a shallow trench isolation (STI) and at least one deep trench isolation (DTI). The first well region of a first conductive type is on the semiconductor substrate. The second well region of a second conductive type is on the semiconductor substrate and adjacent to the first well region. The second conductive type is different from the first conductive type. The active region is on the first well region. The active region has a conductive type the same as the second conductive type of the second well region. The STI is between the first and second well regions. The DTI is below the STI. The DTI is disposed between at least a portion of the first well region and at least a portion of the second well region.

Abstract: A micro-electro-mechanical system (MEMS) chip package including a circuit substrate, a driving chip and a MEMS sensor is provided. The circuit substrate has a first surface and a second surface opposite thereto. The driving chip is embedded within the circuit substrate and includes a first signal transmission electrode, a second signal transmission electrode and a third signal transmission electrode. The MEMS sensor is disposed on the first surface of the circuit substrate. The circuit substrate includes at least one first conductive wiring electrically connected with the first signal transmission electrode and at least one second conductive wiring electrically connected with the second signal transmission electrode. The first conductive wiring is merely exposed at the first surface and the second conductive wiring is merely exposed at the second surface. The MEMS sensor is electrically connected with the first signal transmission electrode through the first conductive wiring.

Abstract: The present disclosure provides a device having a doped active region disposed in a substrate. The doped active region having an elongate shape and extends in a first direction. The device also includes a plurality of first metal gates disposed over the active region such that the first metal gates each extend in a second direction different from the first direction. The plurality of first metal gates includes an outer-most first metal gate having a greater dimension measured in the second direction than the rest of the first metal gates. The device further includes a plurality of second metal gates disposed over the substrate but not over the doped active region. The second metal gates contain different materials than the first metal gates. The second metal gates each extend in the second direction and form a plurality of respective N/P boundaries with the first metal gates.

Abstract: A solid-filled encapsulated LED bulb with a base, at least one LED light source and at least one power supply element includes a transparent solid-filled heat-dissipating light guide member attached and covered onto the LED light source and the power supply element. A side of the heat-dissipating light guide member is packaged with the base to form the LED bulb. The heat of the LED light source is conducted and dissipated to the outside through the heat-dissipating light guide member. A light of the LED light source is outputted with an intensity IA through the heat-dissipating light guide member. The intensity IA of the light and the intensity IB of the LED light source satisfy the condition of (IA/IB)>70%. The use of a conventional dissipating structure is skipped to reduce the production cost and expedite the assembling and packaging processes while maintaining excellent heat dissipation and light output effects.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.

Abstract: A multimedia playing system is provided. A portable electronic device includes a first dock port, a second dock port, a power module, an audio processor and a controller. When a first single-ear wireless earphone connects with the first dock port, the power module charges the first single-ear wireless earphone via the first dock port. When a second single-ear wireless earphone connects with the second dock port, the power module charges the second single-ear wireless earphone via the second dock port. The audio processor provides a left sound channel signal and a right sound channel signal. When the first single-ear wireless earphone separates from the first dock port, the controller provides one of the left sound channel signal and the right sound channel signal to the first single-ear wireless earphone according to a relative position between the first dock port and a user.

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Abstract: A surface treatment of a magnesium alloy includes preparing a substrate of magnesium alloy, micro-arc oxidizing the substrate of magnesium alloy, forming an oxide layer with a hydroxyl group on the substrate of magnesium alloy, silylizing the oxide layer of the substrate of magnesium alloy with the oxide layer, by soaking the substrate of magnesium alloy in a processing solution with a silyl group-containing compound for 1-300 minutes, and placing the substrate of magnesium alloy with the silylized oxide layer at 70-200° C. for 1-300 minutes, allowing a condensation reaction to occur. The manufactured surface-treated magnesium alloy shows a decreased degradation rate in vivo.

Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, an interlayer dielectric, an inter-source layer, an inter-source plug, an inter-drain layer, an inter-drain plug, an inter-gate layer, and an inter-gate plug. The active layer is made of III-V group semiconductors. The source electrode, the drain electrode, and the gate electrode are disposed on the active layer. The gate electrode is disposed between the source electrode and the drain electrode. The interlayer dielectric covers the source electrode, the drain electrode, and the gate electrode. The inter-source layer, the inter-drain layer, and the inter-gate layer are disposed on the interlayer dielectric. The inter-source plug is electrically connected to the source electrode and the inter-source layer. The inter-drain plug is electrically connected to the drain electrode and the inter-drain layer. The inter-gate plug is electrically connected to the gate electrode and the inter-gate layer.

Abstract: An axially symmetric LED light bulb includes a lamp shade, a substrate and a connecting seat. The substrate installed on the connecting seat includes plural LED light sources. The lamp shade has an edge connected to the connecting seat, and the substrate is covered inside the lamp shade. The lamp shade has an unequal thickness with a thicker top and thinner sides. The axially symmetric LED light bulb provides excellent light uniformity and wide-angle illumination.

Abstract: A pixel structure in an organic light emitting display panel includes a plurality of pixels. Each pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. Lengths of the first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged along a first direction. Widths of the first sub-pixel, the second sub-pixel, and the third sub-pixel is arranged along a second direction. A length of the first sub-pixel is greater than a length of the second sub-pixel along the first direction and a length of the third sub-pixel along the first direction. The first sub-pixel, the second sub-pixel, and the third sub-pixel are orderly arranged along the second direction.

Abstract: A plug for provision of power includes a housing forming a receiving cavity with two opposite sites in a vertical direction which is compatible with a standard plug connector with twelve contacts on each site and a first and second rows of contacts on the sides while in diagonally symmetrical manner. Each contact includes a contacting section, and a connecting section for directly connecting to a corresponding wire. Each row of contacts is categorized with a pair of power contacts, a pair of grounding contacts and a specific contact without any high speed differential pair. Two pair of power contacts of both two rows are electrically connected together either via direct mechanical connection via vertical extensions or via indirect electrical connection via the latch which has a pair of side arms extending into the receiving cavity at two opposite transverse ends.

Abstract: A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.

Abstract: A method of forming a contact structure is provided. A silicon-containing substrate is provided with a composite dielectric layer formed thereon. An opening penetrates through the composite dielectric layer and exposes a portion of the source/drain region. A titanium nitride layer is formed in the opening, and the titanium nitride layer is in contact with the exposed portion of the source/drain region. The titanium nitride layer is annealed, so that the bottom portion of the titanium nitride layer is partially transformed into a titanium silicide layer. A conductive layer is formed to fill up the opening.

Abstract: A back side image sensor and method of manufacture are provided. In an embodiment a bottom anti-reflective coating is formed over a substrate, and a metal shield layer is formed over the bottom anti-reflective coating. The metal shield layer is patterned to form a grid pattern over a sensor array region of the substrate, and a first dielectric layer and a second dielectric layer are formed to at least partially fill in openings within the grid pattern.

Abstract: In one aspect of the present disclosure, a semiconductor device includes a channel layer, an AlxIn1-xN layer on the channel layer with a thickness of t1, and a reverse polarization layer on the AlxIn1-xN layer with a thickness of t2. The thickness is 0.5×t1?t2?3×t1. In another aspect of the present disclosure, a method of manufacturing a semiconductor device is provided. The method including: forming a channel layer on a substrate; forming an AlxIn1-xN layer on the channel layer with a thickness of t1; and forming a reverse polarization layer on the AlxIn1-xN layer with a thickness of t2. The thickness is 0.5×t1?t2?3×t1.