Abstract: An integrated circuit structure includes a first conductive line, a dielectric layer over the first conductive line, a diffusion barrier layer in the dielectric layer, and a second conductive line in the dielectric layer. The second conductive line includes a first portion of the diffusion barrier layer. A via is underlying the second conductive line and electrically couples the second conductive line to the first conductive line. The via includes a second portion of the diffusion barrier layer, with the second portion of the diffusion barrier layer having a bottom end higher than a bottom surface of the via.

Abstract: A semiconductor device includes a source/drain feature in a substrate. The source/drain feature has an upper portion and a lower portion, the upper portion having a lower concentration of Ge than the lower portion. A Si-containing layer over the source/drain feature includes a metal silicide layer.

Abstract: An electronic device includes a first module including a first conductive component and a power control unit coupled to the first conductive component. The electronic device further includes a second module, a first hinge for pivoting the second module relative to the first module, and a first arm connected to the first hinge. The power control unit controls whether to execute a first power management status according to whether the first arm contacts the first conductive component as the second module pivots relative to the first module at a first angle by the first hinge.

Abstract: A patch panel structure includes a circuit board, a plurality of first RJ45 sockets, and a plurality of second RJ45 sockets. The circuit board has a first end and a second end opposite to each other. A plurality of first conducting points are formed at the first end. A plurality of second conducting points are formed at the second end. Each of the first RJ45 sockets forms a first interface and is electrically connected to each of the first conducting points. Each of the second RJ45 sockets forms a second interface, is electrically connected to each of the second conducting points, and is disposed in a parallel and symmetrical manner with respect to each of the first RJ45 sockets. Each of the first interfaces of the first RJ45 sockets is disposed in a back-to-back and spaced-apart manner with respect to each of the second RJ45 sockets.

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Abstract: A multi-floor type MEMS microphone includes a housing formed by a stack of circuit boards and provided with a first cavity, a second cavity in vertical communication with the first cavity, and a sound hole in communication with the second cavity. The second cavity has a vertical cross-sectional area smaller than that of the first cavity. A MEMS transducer is disposed in the second cavity and electrically conducted with the housing, and an ASIC chip is disposed in the first cavity and electrically conducted with the housing. By this design, the volume of the back chamber of a vibrating diaphragm of the MEMS transducer can be increased in a limited space of the housing, and thus the sensitivity of the microphone can be improved.

Abstract: A method includes obtaining electronically formatted information about previously performed imaging procedures, classifying the information into groups of protocols based on initially selected protocols for the previously performed imaging procedures and generating data indicative thereof, identifying deviations between the classified information and the corresponding initially selected protocols for the previously performed imaging procedures, and generating a signal indicative of the deviations. A method includes recommending at least one of a plurality of protocols for an imaging procedure based on at least one of a score, a probability, or a pre-determined rule, which is based on extracted medical concepts from patient information and extracted medical concepts from previously imaged patient information, and generating a signal indicative of the recommendation.

Abstract: A cumulative image recognition method performs a matching analysis on frame and matching data in a mobile device when the mobile device focuses on a recognition target and captures frame of the image of the recognition target. The method obtains the feature value of each matching data according to the matching result, and determines if one of the matching data has an optimal result matching the recognition target according to several entries of feature values. If no optimal result, then the method respectively sums up the feature value of each matching data into a summing feature value and determines if the plurality of the matching data has a candidate result similar to the recognition target according to several entries of the summing feature values. If no candidate result, the mobile device captures the next frame on the recognition target, and performs next matching analysis on the next frame.

Abstract: Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device comprises a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. The semiconductor device comprises a guard structure disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region.

Abstract: The present invention features a compound of formula I: or a pharmaceutically acceptable salt thereof, where R1, R2, R3, W, X, Y, Z, n, o, p, and q are defined herein, for the treatment of CFTR mediated diseases, such as cystic fibrosis. The present invention also features pharmaceutical compositions, method of treating, and kits thereof.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a dielectric layer positioned on the semiconductor substrate. The dielectric layer has a first recess. The semiconductor device structure includes a conductive structure filling the first recess. The conductive structure includes a first conductive layer and a second conductive layer. The first conductive layer is positioned over an inner wall and a bottom of the first recess. The first conductive layer has a second recess in the first recess. The second conductive layer fills the second recess. The first conductive layer and the second conductive layer include cobalt. The second conductive layer further includes at least one of sulfur, chlorine, boron, phosphorus, or nitrogen.

Abstract: A method of estimating the capability of a semiconductor manufacturing system is provided. Plural first transistors are formed and a first VtMM value and a first scale value are obtained. Plural second transistors are formed and a second VtMM value and a second scale value are obtained. Plural third transistors are formed and a third VtMM value and a third scale value are obtained. A first channel length of the first transistor is smaller than a second channel length of the second transistor and is equal to a third channel length of the third transistor. A VtMM v.s. scale figure is established. A line is formed by linking the first dot and the third dot and a vertical Gap between the line and the second dot is measured. The capability of the semiconductor system is determined based on the vertical Gap. The invention further provides a chip.

Abstract: BSI image sensors and methods. In an embodiment, a substrate is provided having a sensor array and a periphery region and having a front side and a back side surface; a bottom anti-reflective coating (BARC) is formed over the back side to a first thickness, over the sensor array region and the periphery region; forming a first dielectric layer over the BARC; a metal shield is formed; selectively removing the metal shield from over the sensor array region; selectively removing the first dielectric layer from over the sensor array region, wherein a portion of the first thickness of the BARC is also removed and a remainder of the first thickness of the BARC remains during the process of selectively removing the first dielectric layer; forming a second dielectric layer over the remainder of the BARC and over the metal shield; and forming a passivation layer over the second dielectric layer.

Abstract: A transmission system and a transmission method for network address translation traversal are provided. The transmission system includes a private network device, a network address record device, a public network device and a network address translation server. The network address record device records an inner network address of the private network device and an outer network address corresponding to the inner network address. The public network device inquires the inner network address of the private network device and the outer network address corresponding to the inner network address from the network address record device, and generates a packet according to the inner network address and the outer network address corresponding to the inner network address. The network address translation server receives the packet from the public network device, and transmits the packet to the public network device.

Abstract: A light tunnel for use in an optical projection system, comprising: a plurality of reflecting plates, each said reflecting plate being disposed between and connected to the other two said reflecting plates, so that a light passage with a hollow structure is defined by said plurality of reflecting plates. At least one of said reflecting plates has a first surface in an inclined structure, said reflecting plate having said first surface is disposed between and obliquely connected to the other two said reflecting plates for forming said light passage having a non-rectangular cross section, and said first surface of said reflecting plate is abutted against an adjoined reflecting plate to form a junction with no gap between said first surface of said reflecting plate and said adjoined reflecting plate.

Abstract: The present disclosure provides a wave energy gathering and enhancing device disposed in a setting area of the sea-bed. A seawater wave approaches the wave energy gathering and enhancing device with a wave vector. The wave energy gathering and enhancing device comprises a plurality of structures. The plurality of structures are arranged below the sea surface in a two-dimensional symmetric discrete group. Each of the structures has a top surface and the top surface is located below the sea surface with a predetermined depth. A lattice with a definite lattice constant is formed by the plurality of structures. The lattice plane formed by the structures and the wave vector of the seawater wave form an angle. The structures enhance the amplitude of the seawater wave when the seawater wave interacts with and passes through the structures.

Abstract: In one embodiment, a battery control system, comprising: a plurality of battery units comprising a battery system; and a controller coupled to the plurality of battery units, the controller configured to monitor, for each battery unit, a first voltage and a second voltage, the first voltage corresponding to an absolute value of a shut-off voltage and a second voltage corresponding to a warning voltage, the first voltage smaller than the second voltage, wherein responsive to one of the battery units reaching the second voltage, the controller is configured to provide a first alert before the any of the battery units reaches the first voltage.

Abstract: A self-excited power conversion circuit for secondary side control output power includes a comparator unit and a transistor installed directly in a secondary side output module, and the comparator unit is electrically coupled to at least one load, and the transistor is electrically coupled between to a conversion module of the circuit and the load. The comparator unit is provided for adjusting the duty cycle of the transistor after detecting the amount of energy outputted from the conversion module to the load from, so as to adjust the amount of energy actually received by the load to achieve a constant power effect.

Abstract: A Bluetooth device used for data transmission between first and second peripheral devices is provided. The Bluetooth device includes a processing circuit and a Bluetooth chip configured to be capable of being operated in a transmitting mode and a receiving mode for data transmitting and data receiving, respectively. In the transmitting mode, a first communication link is established between the Bluetooth chip and the first peripheral device through a first communication protocol. The processing circuit establishes a second communication protocol. In the receiving mode, a second communication link is established between the Bluetooth chip and the second peripheral device through a third communication protocol. The second peripheral device transmits a data to the Bluetooth chip through the second communication link and the Bluetooth chip transmits, based on the second communication protocol, the received data to the first peripheral device through the first communication link simultaneously.

Abstract: The present disclosure provides an embodiment of a method for fabricating a three dimensional (3D) image sensor structure. The method includes providing to an image sensor substrate having image sensors formed therein and a first interconnect structure formed thereon, and a logic substrate having a logic circuit formed therein and a second interconnect structure formed thereon; bonding the logic substrate to the image sensor substrate in a configuration that the first interconnect structure and second interconnect structure are sandwiched between the logic substrate and the image sensor substrate; and forming a conductive feature extending from the logic substrate to the first interconnect structure, thereby electrically coupling the logic circuit to the image sensors.