Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.

Abstract: A method for fabricating a substrate structure is provided, which includes the steps of: disposing at least a strengthening member on a carrier; sequentially forming a first circuit layer and a dielectric layer on the carrier, wherein the strengthening member is embedded in the dielectric layer; forming a second circuit layer on the dielectric layer; removing the carrier; and forming an insulating layer on the first circuit layer and the second circuit layer. The strengthening member facilitates to reduce thermal warping of the substrate structure.

Abstract: An electronic device may be provided with wireless circuitry that includes antennas. An antenna may be formed from metal traces on a dielectric antenna carrier. The antenna carrier may be formed by molding a layer of plastic onto the surface of a foam member. The foam member may have a low dielectric constant to enhance antenna performance and may be formed from a stiff closed cell plastic foam material. Heat and pressure may be used to attach the layer of plastic to the surface of the foam member without adhesive. A laser may be used to selectively expose portions of the plastic layer to laser light. The plastic layer may include additives that sensitize the plastic layer to light exposure. Electroplated metal traces for the antenna may be formed on the exposed portions of the plastic layer while leaving other portions of the plastic layer uncovered with metal.

Abstract: A head-mounted display device includes a wearable device, a display mainframe and a pivoting mechanism. The display mainframe includes a cover body and a display-receiving portion connected to one side of the cover body. The cover body is provided with a light transmissive area and an accommodation area in which the light transmissive area is arranged between the accommodation area and the display-receiving portion. The pivoting mechanism is pivotally connected to the wearable device and the display mainframe.

Abstract: A method for fabricating a substrate structure is provided, which includes the steps of: disposing at least a strengthening member on a carrier; sequentially forming a first circuit layer and a dielectric layer on the carrier, wherein the strengthening member is embedded in the dielectric layer; forming a second circuit layer on the dielectric layer; removing the carrier; and forming an insulating layer on the first circuit layer and the second circuit layer. The strengthening member facilitates to reduce thermal warping of the substrate structure.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, agate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure, adjacent to the gate structure. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is formed in the interlayer dielectric layer, wherein the first plug is electrically connected to the epitaxial layer. The protection layer is disposed between the first plug and the gate structure.

Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.

Abstract: A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.

Abstract: The present invention provides a method for forming an opening, including: first, a hard mask material layer is formed on a target layer, next, a tri-layer hard mask is formed on the hard mask material layer, where the tri-layer hard mask includes an bottom organic layer (ODL), a middle silicon-containing hard mask bottom anti-reflection coating (SHB) layer and a top photoresist layer, and an etching process is then performed, to remove parts of the tri-layer hard mask, parts of the hard mask material layer and parts of the target layer in sequence, so as to form at least one opening in the target layer, where during the step for removing parts of the hard mask material layer, a lateral etching rate of the hard mask material layer is smaller than a lateral etching rate of the ODL.

Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, a germanium layer, an interlayer dielectric layer and a first plug. The fin shaped structure is disposed on a substrate. The gate structure is formed across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure adjacent to the gate structure. The germanium layer is disposed on the epitaxial layer. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is disposed in the interlayer dielectric layer to contact the germanium layer.

Abstract: A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, agate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure, adjacent to the gate structure. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is formed in the interlayer dielectric layer, wherein the first plug is electrically connected to the epitaxial layer. The protection layer is disposed between the first plug and the gate structure.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure on the substrate; an interlayer dielectric (ILD) around the gate structure; a first contact plug in the ILD layer; a second dielectric layer on the ILD layer; a second contact plug in the second dielectric layer and electrically connected to the first contact plug; and a spacer between the second contact plug and the second dielectric layer.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure; forming a sacrificial layer on the gate structure; forming a first contact plug in the sacrificial layer and the ILD layer; removing the sacrificial layer; and forming a first dielectric layer on the gate structure and the first contact plug.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure and a second gate structure on the substrate; forming a contact etch stop layer (CESL) on the first gate structure, the second gate structure, and the substrate; removing part of the CESL between the first gate structure and the second gate structure; and forming an interlayer dielectric (ILD) layer on the CESL.

Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, a germanium layer, an interlayer dielectric layer and a first plug. The fin shaped structure is disposed on a substrate. The gate structure is formed across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure adjacent to the gate structure. The germanium layer is disposed on the epitaxial layer. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is disposed in the interlayer dielectric layer to contact the germanium layer.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.

Abstract: A waterproof electronic device that is waterproof and has pressure-equilibrium functions is provided. The waterproof electronic device includes a housing, a microphone, an elastic element, and a waterproof element. The housing has a chamber and an acoustic hole communicating with the chamber. The microphone is disposed in the chamber. The elastic element is disposed on the microphone. The elastic element includes a through hole facing the microphone, and a ventilation groove communicating with the through hole. The waterproof element is connected to the elastic element and the housing, and is configured to block liquid. The waterproof element includes pores communicating with the acoustic hole and the through hole.

Abstract: A method for manufacturing a semiconductor device having metal gates includes following steps. A substrate including a first transistor and a second transistor formed thereon is provided. The first transistor includes a first gate trench and the second transistor includes a second gate trench. A patterned first work function metal layer is formed in the first gate trench and followed by forming a second sacrificial masking layer respectively in the first gate trench and the second gate trench. An etching process is then performed to form a U-shaped first work function metal layer in the first gate trench. Subsequently, a two-step etching process including a strip step and a wet etching step is performed to remove the second sacrificial masking layer and portions of the U-shaped first work function metal layer to form a taper top on the U-shaped first work function metal layer in the first gate trench.