Patents by Inventor Chun Wen
Chun Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11660754Abstract: A detection system and detection method for the sensors of a robot. A detection system installs three sensors at the motor side and power output terminal of the robot. A detection unit detects the normal or abnormal state of three sensors to index the abnormal sensor for maintenance, and two normal sensors are selected for keeping the robot safety operation without stop.Type: GrantFiled: January 19, 2021Date of Patent: May 30, 2023Assignee: TECHMAN ROBOT INC.Inventors: Chun-Wen Lai, I-Bing Su
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Patent number: 11649162Abstract: Various embodiments of the present disclosure are directed towards a method for manufacturing a microelectromechanical systems (MEMS) device. The method includes forming a particle filter layer over a carrier substrate. The particle filter layer is patterned while the particle filter layer is disposed on the carrier substrate to define a particle filter in the particle filter layer. A MEMS substrate is bonded to the carrier substrate. A MEMS structure is formed over the MEMS substrate.Type: GrantFiled: March 5, 2021Date of Patent: May 16, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hua Chu, Chun-Wen Cheng, Wen Cheng Kuo
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Patent number: 11632997Abstract: A headband adjustment structure includes a base, a wearing unit, a rotary adjusting assembly, a linkage member and an elastic element. The wearing unit includes a first end portion and a second end portion that overlap with each other. The first end portion and the second end portion are movably located in the base to define an adjustable accommodation space. The rotary adjusting assembly is pivotally located within the base, and provided with a gear body meshed with a first toothed rack of the first end portion and a second toothed rack of the second end portion so as to simultaneously move the first end portion and the second end portion in opposite directions for adjusting the adjustable accommodation space. The linkage member is connected to the rotary adjusting assembly. The elastic element abutting against the linkage member and the base, respectively.Type: GrantFiled: July 15, 2020Date of Patent: April 25, 2023Assignee: QUANTA COMPUTER INC.Inventors: Chun-Wen Wang, Chun-Nan Huang, Chun-Lung Chen, Heng-Min Hu
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Publication number: 20230081170Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.Type: ApplicationFiled: October 31, 2022Publication date: March 16, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Alexander KALNITSKY, Yi-Shao LIU, Kai-Chih LIANG, Chia-Hua CHU, Chun-Ren CHENG, Chun-Wen CHENG
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Publication number: 20230058133Abstract: A position detection module and a position detection system thereof are provided. The position detection module includes a first output port, a second output port, a third output port and a fourth output port. The first output port outputs a first detection signal, the second output port outputs a first position signal, the third output port outputs a second detection signal, and the fourth output port outputs a second position signal. Thus, the design of two sets of detection signals and position signals enables the position detection module to be fault-tolerant for meeting the requirements of safe dual-channel.Type: ApplicationFiled: March 25, 2022Publication date: February 23, 2023Inventors: Chun-Wen LAI, Chih-Jan KAO, Yen-Chou LU
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Patent number: 11586304Abstract: A digital-pointer interaction system is provided, which includes a display apparatus, a host, a wireless receiving device, and a plurality of wireless pointer devices. The host plays a display screen on the display apparatus, and executes a digital-pointer application. The digital-pointer application renders a plurality of pointer cursors on the display screen according to a number of wireless pointer devices connected to the wireless receiving device, and each wireless pointer device corresponds to each pointer cursor. Each wireless pointer device periodically emits an indication signal to the wireless receiving device, and the wireless receiving device transmits the indication signal to the host. The indication signal includes displacement information of each wireless pointer device. The digital-pointer application controls movement of each pointer cursor on the display screen according to the displacement information of each wireless pointer device.Type: GrantFiled: October 12, 2021Date of Patent: February 21, 2023Assignee: ACER INCORPORATEDInventors: Chun-Wen Wang, Shu-Kuo Kao, Chao-Kuang Yang, Chien-Shan Wang, Shu-Wei Yeh, Chi-Hsiu Kao
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Patent number: 11577954Abstract: A method for forming a MEMS device includes following operations. A first semiconductor layer is formed over a substrate. A plurality of first pillars are formed over the first layer. A second layer is formed over the first pillars and the first layer. A plurality of second pillars are formed over the second layer. A third layer is formed over the second pillars and the second layer.Type: GrantFiled: December 7, 2020Date of Patent: February 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chen Hsiung Yang, Chun-Wen Cheng, Chia-Hua Chu, En-Chan Chen
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Patent number: 11581476Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a first piezoelectric layer, and a first dummy layer. The first piezoelectric layer is over the substrate, and the first piezoelectric layer has a first top surface. The first dummy layer is over the first piezoelectric layer, and the first dummy layer has a second top surface. And an average roughness of the first top surface is greater than an average roughness of the second top surface. A method for manufacturing the semiconductor structure is also provided.Type: GrantFiled: March 13, 2020Date of Patent: February 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun-Wen Cheng, Chun Yin Tsai, Chia-Hua Chu
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Publication number: 20230043512Abstract: A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.Type: ApplicationFiled: October 26, 2022Publication date: February 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Wen Lin, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Che-Wei Hsu
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Patent number: 11555996Abstract: A method for analyzing 2D material thin film and a system for analyzing 2D material thin film are disclosed. The detection method includes the following steps: capturing sample images of 2D material thin films; measuring the 2D material thin films by a Raman spectrometer; performing a visible light hyperspectral algorithm on the sample images by a processor to generate a plurality of visible light hyperspectral images; performing a training and validation procedure, performing an image feature algorithm on the visible light hyperspectral images, and establishing a thin film prediction model based on a validation; and capturing a thin-film image to be measured by the optical microscope, performing the visible light hyperspectral algorithm, and then generating a distribution result of the thin-film image to be measured according to an analysis of the thin film prediction model.Type: GrantFiled: April 20, 2021Date of Patent: January 17, 2023Assignee: NATIONAL CHUNG CHENG UNIVERSITYInventors: Hsiang-Chen Wang, Kai-Chun Li, Kai-Hsiang Ke, Chun-Wen Liang
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Publication number: 20220415699Abstract: Disclosed is a vacuum chuck and a method for securing a warped semiconductor substrate during a semiconductor manufacturing process so as to improve its flatness during a semiconductor manufacturing process. For example, a semiconductor manufacturing system includes: a vacuum chuck configured to hold a substrate, wherein the vacuum chuck comprises, a plurality of vacuum grooves located on a top surface of the vacuum chuck, wherein the top surface is configured to face the substrate; and a plurality of flexible seal rings disposed on the vacuum chuck and extending outwardly from the top surface, wherein the plurality of flexible seal rings are configured to directly contact a bottom surface of the substrate and in adjacent to the plurality of vacuum grooves so as to form a vacuum seal between the substrate and the vacuum chuck, and wherein each of the plurality of flexible seal rings has a zigzag cross section.Type: ApplicationFiled: August 8, 2022Publication date: December 29, 2022Inventors: Chien-Fa LEE, Chin-Lin CHOU, Shang-Ying TSAI, Shou-Wen KUO, Kuei-Sung CHANG, Jiun-Rong PAI, Hsu-Shui LIU, Chun-Wen CHENG
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Patent number: 11533565Abstract: A MEMS microphone includes a substrate having an opening, a first diaphragm, a first backplate, a second diaphragm, and a backplate. The first diaphragm faces the opening in the substrate. The first backplate includes multiple accommodating-openings and it is spaced apart from the first diaphragm. The second diaphragm joints the first diaphragm together at multiple locations by pillars passing through the accommodating-openings in the first backplate. The first backplate is located between the first diaphragm and the second diaphragm. The second backplate includes at least one vent hole and it is spaced apart from the second diaphragm. The second diaphragm is located between the first backplate and the second backplate.Type: GrantFiled: June 17, 2021Date of Patent: December 20, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Wen Cheng, Chia-Hua Chu, Wen-Tuan Lo
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Publication number: 20220380208Abstract: A stacked semiconductor structure includes a first substrate. A multilayer interconnect is disposed over the first substrate. Metal sections are disposed over the multilayer interconnect. First bonding features are over the metal sections. A second substrate has a front surface. A cavity extends from the front surface into a depth D in the second substrate. A movable structure is disposed over the front surface of the second substrate and suspending over the cavity. The movable structure includes a dielectric membrane, metal units over the dielectric membrane and a cap dielectric layer over the metal units. Second bonding features are over the cap dielectric layer and bonded to the first bonding features. The second bonding features extend through the cap dielectric layer and electrically coupled to the metal units.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Inventors: Chia-Hua Chu, Chun-Wen Cheng
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Patent number: 11508608Abstract: Disclosed is a vacuum chuck and a method for securing a warped semiconductor substrate during a semiconductor manufacturing process so as to improve its flatness during a semiconductor manufacturing process. For example, a semiconductor manufacturing system includes: a vacuum chuck configured to hold a substrate, wherein the vacuum chuck comprises, a plurality of vacuum grooves located on a top surface of the vacuum chuck, wherein the top surface is configured to face the substrate; and a plurality of flexible seal rings disposed on the vacuum chuck and extending outwardly from the top surface, wherein the plurality of flexible seal rings are configured to directly contact a bottom surface of the substrate and in adjacent to the plurality of vacuum grooves so as to form a vacuum seal between the substrate and the vacuum chuck, and wherein each of the plurality of flexible seal rings has a zigzag cross section.Type: GrantFiled: August 20, 2020Date of Patent: November 22, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Fa Lee, Chin-Lin Chou, Shang-Ying Tsai, Shou-Wen Kuo, Kuei-Sung Chang, Jiun-Rong Pai, Hsu-Shui Liu, Chun-wen Cheng
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Patent number: 11505454Abstract: A method for manufacturing a MEMS structure is provided. The method includes providing a MEMS substrate having a first surface, forming a first buffer layer on the first surface of the MEMS substrate, and forming a first roughening layer on the first buffer layer. Also, a MEMS structure is provided. The MEMS structure includes a MEMS substrate, a first buffer layer, a first roughening layer, and a CMOS substrate. The MEMS substrate has a first surface and a pillar is on the first surface. The first buffer layer is on the first surface. The first roughening layer is on the first buffer layer. The CMOS substrate has a second surface and is bonded to the MEMS substrate via the pillar. Moreover, an air gap is between the first roughening layer and the second surface of the CMOS substrate.Type: GrantFiled: September 25, 2019Date of Patent: November 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kang-Che Huang, Yi-Chien Wu, Shiang-Chi Lin, Jung-Huei Peng, Chun-Wen Cheng
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Publication number: 20220369041Abstract: A MEMS device and a method of manufacturing the same are provided. A semiconductor device includes a substrate; and a membrane over the substrate and configured to generate charges in response to an acoustic wave, the membrane being in a polygonal shape including vertices. The membrane includes a via pattern having first lines that partition the membrane into slices and extend to the vertices of the membrane such that the slices are separated from each other near an anchored region of the membrane and connected to each other around a central region. The via pattern further includes second lines extending from the anchored region of the membrane toward the central region of the membrane. Each of the second lines includes a length less than a length of each of the first lines.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Inventors: CHUN-WEN CHENG, CHUN YIN TSAI, CHIA-HUA CHU
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Patent number: 11498832Abstract: A stacked semiconductor structure includes a first substrate. A multilayer interconnect is disposed over the first substrate. Metal sections are disposed over the multilayer interconnect. First bonding features are over the metal sections. A second substrate has a front surface. A cavity extends from the front surface into a depth D in the second substrate. A movable structure is disposed over the front surface of the second substrate and suspending over the cavity. The movable structure includes a dielectric membrane, metal units over the dielectric membrane and a cap dielectric layer over the metal units. Second bonding features are over the cap dielectric layer and bonded to the first bonding features. The second bonding features extend through the cap dielectric layer and electrically coupled to the metal units.Type: GrantFiled: May 21, 2018Date of Patent: November 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Hua Chu, Chun-Wen Cheng
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Patent number: 11495607Abstract: Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.Type: GrantFiled: August 7, 2018Date of Patent: November 8, 2022Assignee: Texas Instruments IncorporatedInventors: Huang-Chun Wen, Richard Allen Bailey, Antonio Guillermo Acosta, John A. Rodriguez, Scott Robert Summerfelt, Kemal Tamer San
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Patent number: 11488909Abstract: A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.Type: GrantFiled: July 31, 2020Date of Patent: November 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Wen Lin, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Che-Wei Hsu
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Patent number: 11486854Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.Type: GrantFiled: December 26, 2019Date of Patent: November 1, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Alexander Kalnitsky, Yi-Shao Liu, Kai-Chih Liang, Chia-Hua Chu, Chun-Ren Cheng, Chun-Wen Cheng