Abstract: A diode includes a substrate, a first insulating layer, a second insulating layer, a well, a deep doped region, a first doped region, and a second doped region. The first insulating layer is disposed on the substrate. The second insulating layer is disposed on the substrate, and defines a cell region with the first insulating layer. The well is disposed on the substrate and beneath the cell region. The deep doped region is disposed in the well and beneath the cell region. The first doped region is disposed in the cell region and on the deep doped region. The second doped region is disposed adjacent to the first doped region. The second doped region is disposed on the deep doped region, and is electrically isolated from the well through the deep doped region and the first doped region.

Abstract: The present disclosure provides various molecular constructs having a targeting element and an effector element. Methods for treating various diseases using such molecular constructs are also disclosed.

Abstract: A power rail clamp circuit is coupled between a system power supply and a ground for alleviating an electrostatic discharge effect. The power rail clamp circuit includes a first conduction circuit, a second conduction circuit, an AND gate module and a switch module. The AND gate module receives a first conduction signal generated by the first conduction circuit and a second conduction signal generated by the second conduction circuit to generate an enabling signal. The switch module conducts the power rail clamp circuit according to the enabling signal, to process an electrostatic discharge operation. The first conduction circuit is operated to prevent a high voltage value of the system power supply, and the second conduction circuit is operated to prevent a short initiation period of the system power supply.

Abstract: The present disclosure provides various molecular constructs having a targeting element and an effector element. Methods for treating various diseases using such molecular constructs are also disclosed.

Abstract: A photomask and method for fabricating an integrated circuit is provided. A design layout is provided, wherein the design layout has a plurality of main features. A plurality of assistant features are added in an assistant region of the design layout to form a first layout, wherein the assistant region has no main feature and a width of the assistant region is larger than five times of a width of the main feature. A plurality of optical proximity correction (OPC) features are added on the first layout to form a second layout. And a photomask is formed according to the second layout.

Abstract: An electrostatic discharge (ESD) protection circuit for providing ESD paths between a signal pad and a first or second power rail includes a first ESD protection module and a second ESD protection module. The first ESD protection module is coupled between the signal pad and the first power rail, and includes at least two first diodes and a first resistor. The first diodes are stacked with each other, and one of the first diodes is electrically connected with the first resistor in parallel. The second ESD protection module is coupled between the signal pad and the second power rail, and includes at least two second diodes and a second resistor. The second diodes are stacked with each other, and one of the second diodes is electrically connected with the second resistor in parallel. The signal pad is coupled between the stacked first diodes and the stacked second diodes.

Abstract: A light-emitting device is provided. The light-emitting device comprises: a semiconductor structure comprising a first type semiconductor layer, a second type semiconductor layer, and an active layer between the first type semiconductor layer and the second type semiconductor layer; and an isolation region through the second type semiconductor and the active layer to separate the semiconductor structure into a first part and a second part on the first substrate; wherein the second part functions as a low-resistance resistor and loses its make diode behavior, the active layer in the first part is capable of generating light, and the active layer in the second part is incapable of generating light.

Abstract: The present disclosure is related to an optoelectronic device comprising a semiconductor stack comprising a first surface and a second surface opposite to the first surface; a first contact layer on the first surface; and a second contact layer on the second surface, wherein the second contact layer is not overlapped with the first contact layer in a vertical direction; wherein the second contact layer comprises a plurality of dots separating to each other and formed of semiconductor material.

Abstract: A light-emitting device comprises a carrier; a first semiconductor element formed on the carrier and comprising a first semiconductor structure and a second semiconductor structure, wherein the second semiconductor structure is closer to the carrier than the first semiconductor structure is, the first semiconductor structure comprises a first active layer emitting a first light having a first dominant wavelength during a normal operation, and the second semiconductor structure comprises a second active layer; and a bridge on a side surface of the second active layer of the second semiconductor structure.

Abstract: An electroluminescent (EL) device is disclosed. An optically reflective concave structure includes a first surface and a second surface that lies at an angle relative to the first surface, wherein at least the first and second surfaces are optically reflective. One or more functional layers include a light emitting layer, disposed over the surfaces of the optically reflective concave structure, wherein at least one electroluminescent area of the light emitting layer is defined on the first surface. Especially, the ratio between the diameter of the first surface and the thickness of the one or more functional layers in the optically reflective concave structure is smaller than a constant value.

Abstract: A light-emitting device comprises a carrier; and a first semiconductor element comprising a first semiconductor structure and a second semiconductor structure, wherein the second semiconductor structure is closer to the carrier than the first semiconductor structure is to the carrier, the first semiconductor structure comprises a first MQW structure configured to emit a first light having a first dominant wavelength during normal operation, and the second semiconductor structure comprises a second MQW structure configured not to emit light during normal operation.

Abstract: The present disclosure provides a light-emitting device, comprising: a light-emitting stack; a first semiconductor layer on the light-emitting stack; a first electrode formed on the first semiconductor layer and comprising an inner segment, an outer segment, and a plurality of extending segments electrically connecting the inner segment with the outer segment.

Abstract: A semiconductor light-emitting device comprises a substrate; a first adhesive layer on the substrate; multiple epitaxial units on the first adhesive layer; a second adhesive layer on the multiple epitaxial units; multiple first electrodes between the first adhesive layer and the multiple epitaxial units, and contacting the first adhesive layer and the multiple epitaxial units; and multiple second electrodes between the second adhesive layer and the multiple epitaxial units, and contacting the second adhesive layer and the multiple epitaxial units; wherein the multiple epitaxial units are totally separated.

Abstract: A silicon controlled rectifier including a semiconductor substrate, first and second semiconductor wells, first and second semiconductor regions, third and fourth semiconductor regions and a silicide layer is provided. The first and the second semiconductor wells are formed in the semiconductor substrate. The first and the second semiconductor regions are respectively formed in the first and the second semiconductor wells in spaced apart relation. The third and the fourth semiconductor regions are respectively formed in the first and the second semiconductor wells. The silicide layer is formed on the third and the fourth semiconductor regions. The silicon controlled rectifier is at least suitable for high frequency circuit application. The silicon controlled rectifier has a relatively low trigger voltage, a relatively high electrostatic discharge level, and a relatively low capacitance.

Abstract: An electronic static discharge protection apparatus provided. A plurality of ESD circuits serially coupled between a pad and a internal circuit, a first stage ESD circuit includes a ESD element directly coupled to the pad, and a last stage ESD circuit includes an inductive element directly coupled to the internal circuit, so as to improve electronic discharge protecting ability of the ESD protection apparatus and increase circuit operation bandwidth without signal loss attenuation.

Abstract: The present disclosure provides a method for manufacturing a light-emitting device, comprising: providing a first substrate; providing a semiconductor stack on the first substrate, the semiconductor stack comprising a first conductive type semiconductor layer, a light-emitting layer on the first conductive type semiconductor layer, and a second conductive type semiconductor layer on the light-emitting layer, wherein the semiconductor stack comprises a plurality of blocks of semiconductor stack separated from each other, and wherein the plurality of blocks of semiconductor stack comprise a first block of semiconductor stack and a second block of semiconductor stack; performing a separating step to separate the first block of semiconductor stack from the first substrate, and the second block of semiconductor stack remained on the first substrate; providing a permanent substrate comprising a first surface, a second surface, and a third block of semiconductor stack on the first surface; and bonding one of the fir

Abstract: A light-emitting element, comprises a light-emitting stack comprising an active layer; a window layer on the light-emitting stack, wherein the window layer has a surface opposite to the light-emitting stack; and an insulative layer on the surface, wherein the surface comprises a cavity and the insulative layer substantially conformally covering the cavity, and wherein the insulative layer has a first refractive index equal to or smaller than 1.4.

Abstract: A frequency selecting module for a touch system includes a storage unit, for storing a sum of at least one of a plurality of sensing signals of a plurality sensing channels in the touch system; a spectrum calculating unit, for transforming the sum of the at least one of the plurality of sensing signals stored in the storage unit to generate a spectrum data and storing the spectrum data to the storage unit; and a selecting unit, for generating an adjusting signal according to the spectrum data to select one of a plurality of operation frequencies as a working frequency of the plurality of sensing signals.

Abstract: The present disclosure provides a light-emitting device, comprising: a light-emitting stack comprising an active layer, wherein the active layer is configured to emit light; a first semiconductor layer on the light-emitting stack; a first electrode formed on the first semiconductor layer and comprising an inner segment, an outer segment, and a plurality of extending segments electrically connecting the inner segment with the outer segment; and a light-absorbing layer having a first portion surrounding the first semiconductor layer in a top view.

Abstract: A gate-bounded silicon controlled rectifier includes a substrate, an N-type well region, a P-type well region, a first N-type semiconductor region, a first P-type semiconductor region, a second N-type semiconductor region, a second P-type semiconductor region and a third semiconductor region. The N-type well region and the P-type well region are disposed in the substrate. The first N-type semiconductor region is disposed in the N-type well region. The first P-type semiconductor region is disposed in the P-type well region. The second N-type semiconductor region is disposed in the P-type well region and located between the first N-type semiconductor region and the first P-type semiconductor region. The second P-type semiconductor region is disposed in the N-type well region and located between the first N-type semiconductor region and the first P-type semiconductor region. The third semiconductor region is located between the second N-type semiconductor region and the second P-type semiconductor region.