Patents by Inventor Ding Wang

Ding Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for making a carbon nanotube film
    Patent number: 8808589
    Abstract: A method for making a carbon nanotube film includes the steps of: (a) adding a plurality of carbon nanotubes to a solvent to create a carbon nanotube floccule structure in the solvent; (b) separating the carbon nanotube floccule structure from the solvent; and (c) shaping the separated carbon nanotube floccule structure to obtain the carbon nanotube film.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: August 19, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Ding Wang, Chang-Hong Liu, Shou-Shan Fan
  • Delamination resistance of stacked dies in die saw
    Patent number: 8803332
    Abstract: An integrated circuit structure includes a first die including TSVs; a second die over and bonded to the first die, with the first die having a surface facing the second die; and a molding compound including a portion over the first die and the second die. The molding compound contacts the surface of the second die. Further, the molding compound includes a portion extending below the surface of the second die.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-I Lee, Tsung-Ding Wang
  • Package structures and methods for forming the same
    Patent number: 8803323
    Abstract: A device includes a first package component and the second package component. The first package component includes a first plurality of connectors at a top surface of the first package component, and a second plurality of connectors at the top surface. The second package component is over and bonded to the first plurality of connectors, wherein the second plurality of connectors is not bonded to the second package component. A solder resist is on the top surface of the first package component. A trench is disposed in the solder resist, wherein a portion of the trench spaces the second plurality of connectors apart from the first plurality of connectors.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jiun Yi Wu, Tsung-Ding Wang
  • Method of Forming Wafer-Level Molded Structure for Package Assembly
    Publication number: 20140206140
    Abstract: A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer. The bottom wafer, the top dies, and the first molding material are sawed to form molding units. Each of the molding units includes one of the top dies and a bottom die sawed from the bottom wafer. The molding units are bonded onto a package substrate and a second molding material is molding onto the one of the molding units and the package substrate. Thereafter, the package substrate and the second molding material are sawed to form package-molded units.
    Type: Application
    Filed: March 25, 2014
    Publication date: July 24, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Ding Wang, Bo-I Lee, Chien-Hsun Lee
  • PACKAGE ON PACKAGE STRUCTURES AND METHODS FOR FORMING THE SAME
    Publication number: 20140197547
    Abstract: A method of forming a semiconductor device package includes removing a portion of a first connector and a molding compound surrounding the first connector to form an opening, wherein the first connector is part of a first package, and removing the portion of the first connector comprises forming a surface on the first connector which is at an angle with respect to a top surface of the molding compound. The method further includes placing a second connector in the opening, wherein the second connector is part of a second package having a semiconductor die. The method further includes bonding the second connector to a remaining portion of the first connector.
    Type: Application
    Filed: March 14, 2014
    Publication date: July 17, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung Wei CHENG, Tsung-Ding WANG, Chien-Hsun LEE, Chun-Chih CHUANG
  • Method for making a carbon nanotube film
    Publication number: 20140199855
    Abstract: A method for making a carbon nanotube film includes the steps of: (a) adding a plurality of carbon nanotubes to a solvent to create a carbon nanotube floccule structure in the solvent; (b) separating the carbon nanotube floccule structure from the solvent; and (c) shaping the separated carbon nanotube floccule structure to obtain the carbon nanotube film.
    Type: Application
    Filed: December 20, 2007
    Publication date: July 17, 2014
    Applicants: HON HAI Precision Industry CO., LTD., Tsinghua University
    Inventors: Ding Wang, Chang-Hong Liu, Shou-Shan Fan
  • Optical Connector Having A Plurality Of Optical Fibres With Staggered Cleaved Ends Coupled To Associated Microlenses
    Publication number: 20140193124
    Abstract: The disclosure generally relates to sets of optical waveguides such as optical fiber ribbons, and fiber optic connectors useful for connecting multiple optical fibers to other optical fibres or optical devices. In particular, the disclosure provides an efficient, compact and reliable optical fiber connector (100) that incorporates an optically transmissive substrate (120) receiving the optical fibers (132) in V-grooves on a first major surface thereof with their angle cleaved ends (126) arranged in a staggered arrangement so as to redirect light to an associated microlens (128) at the opposite surface of the transparent substrate (120).
    Type: Application
    Filed: September 12, 2012
    Publication date: July 10, 2014
    Applicant: 3M INNOVATIVE PROPERITEIS COMPANY
    Inventors: James R. Bylander, Ding Wang
  • OPTICAL SUBSTRATE HAVING A PLURALITY OF STAGGERED LIGHT REDIRECTING FEATURES ON A MAJOR SURFACE THEREOF
    Publication number: 20140193116
    Abstract: The disclosure generally relates to sets of optical waveguides such as optical fiber ribbons, and fiber optic connectors useful for connecting multiple optical fibers. In particular, the disclosure provides an efficient, compact, and reliable optical fiber connector that incorporates a unitary substrate comprising a plurality of staggered light redirecting features on an input surface there of directing incoming light from optical fibres through the substrate towards optical elements to be coupled with.
    Type: Application
    Filed: September 13, 2012
    Publication date: July 10, 2014
    Applicant: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: James R. Bylander, Ding Wang
  • POST-PASSIVATION INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME
    Publication number: 20140183725
    Abstract: A semiconductor device includes a passivation layer formed on a semiconductor substrate, a protective layer overlying the passivation layer and having an opening, an interconnect structure formed in the opening of the protective layer, a bump formed on the interconnect structure, and a molding compound layer overlying the interconnect structure and being in physical contact with a lower portion of the bump.
    Type: Application
    Filed: May 30, 2013
    Publication date: July 3, 2014
    Inventors: Hung-Jen Lin, Tsung-Ding Wang, Chien-Hsun Lee
  • Wafer-level molded structure for package assembly
    Patent number: 8743561
    Abstract: An integrated circuit structure includes a bottom die; a top die bonded to the bottom die with the top die having a size smaller than the bottom die; and a molding compound over the bottom die and the top die. The molding compound contacts edges of the top die. The edges of the bottom die are vertically aligned to respective edges of the molding compound.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Ding Wang, Bo-I Lee, Chien-Hsiun Lee
  • POP Structures with Air Gaps and Methods for Forming the Same
    Publication number: 20140131894
    Abstract: A device includes a bottom package component that includes a bottom die, and a dam over a top surface of the bottom die. The dam has a plurality of sides forming a partial ring, with an air gap surrounded by the plurality of side portions. The air gap overlaps the bottom die. A top package component is bonded to the bottom package component, wherein the air gap separates a bottom surface of the top package component from the bottom die.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 15, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Tsung-Ding Wang, Chen-Shien Chen, Chung-Shi Liu, Jiun Yi Wu
  • Molded Underfilling for Package on Package Devices
    Publication number: 20140124916
    Abstract: Presented herein are a package-on-package device having a molded underfill and a method for forming the same, the method comprising applying a package mount mounting a die to the first side of a carrier package. A molded underfill may be applied first side of the carrier package, and be in contact with a portion of the package mount a portion of a sidewall of the die. A top package having at least one land may be mounted to the first side of the carrier package above the die, and, optionally separated from the top of the die. The package mount may be coined prior to, during or after applying the molded underfill to optionally be level with the underfill surface. The underfill region contacting the package mount may be below or above the surface of the underfill region contacting the die sidewall.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Chien-Hsun Lee, Jung Wei Cheng, Tsung-Ding Wang, Ming-Da Cheng, Yung Ching Chen
  • Package on package structures and methods for forming the same
    Patent number: 8704354
    Abstract: The described embodiments of forming bonding structures for package on package involves removing a portion of connectors and molding compound of the lower package. The described bonding mechanisms enable easier placement and alignment of connectors of an upper package to with connector of a lower package. As a result, the process window of the bonding process is wider. In addition, the bonding structures have smoother join profile and planar joint plane. As a result, the bonding structures are less likely to crack and also are less likely to crack. Both the yield and the form factor of the package on package structure are improved.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung Wei Cheng, Tsung-Ding Wang, Chien-Hsun Lee, Chun-Chih Chuang
  • Cooling Channels in 3DIC Stacks
    Publication number: 20140103540
    Abstract: An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.
    Type: Application
    Filed: December 18, 2013
    Publication date: April 17, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Ching, Ching-Wen Hsiao, Tsung-Ding Wang, Ming Hung Tseng, Chen-Shien Chen
  • Solar collector and solar heating system using same
    Patent number: 8695586
    Abstract: A solar collector includes a substrate having a top surface and a bottom surface opposite to the upper surface, a sidewall, a transparent cover, and a heat-absorbing layer. The sidewall is arranged on the top surface of the substrate. The transparent cover is disposed on the sidewall opposite to the substrate to form a sealed chamber with the substrate together. The heat-absorbing layer is disposed on the upper surface of the substrate and includes a carbon nanotube film having a plurality of carbon nanotubes. The carbon nanotubes in the carbon nanotube film are entangled with each other.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: April 15, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Peng Liu, Pi-Jin Chen, Liang Liu, Kai-Li Jiang, Ding Wang, Chang-Hong Liu, Shou-Shan Fan
  • Packaging jig and process for semiconductor packaging
    Patent number: 8691629
    Abstract: An embodiment is a method for semiconductor packaging. The method comprises attaching a chip to a carrier substrate through a first side of a jig, the chip being attached by bumps; applying balls to bond pads on the carrier substrate through a second side of the jig; and simultaneously reflowing the bumps and the balls. According to a further embodiment, a packaging jig comprises a cover, a base, and a connector. The cover has a first window through the cover. The base has a second window through the base. The first window exposes a first surface of a volume intermediate the cover and the base, and the second window exposes a second surface of the volume. The first surface is opposite the volume from the second surface. The connector aligns and couples the cover to the base.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Huang, Tsung-Ding Wang
  • Mold chase design for package-on-package applications
    Patent number: 8658464
    Abstract: A method includes placing a mold chase over a bottom package, wherein the bottom package has a connector at a top surface of the bottom package. The mold chase includes a cover, and a pin under and connected to the cover. The pin occupies a space extending from a top surface of the connector to the cover. A polymer is filled into a space between the cover of the mold chase and the bottom package. The polymer is then cured. After the step of curing the polymer, the mold chase is removed, and the connector is exposed through an opening in the polymer, wherein the opening is left by the pin of the mold chase.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: February 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung Wei Cheng, Chien-Hsiun Lee, Tsung-Ding Wang, Chun-Chih Chuang
  • SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20140048926
    Abstract: A semiconductor package includes a passivation layer overlying a semiconductor substrate, a bump overlying the passivation layer, and a molding compound layer overlying the passivation layer and covering a lower portion of the bump. A sidewall of the passivation layer is covered by the molding compound layer.
    Type: Application
    Filed: August 14, 2012
    Publication date: February 20, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Ding WANG, Jung Wei CHENG, Bo-I LEE
  • SYSTEM IN PACKAGE AND METHOD OF FABRICATING SAME
    Publication number: 20140042623
    Abstract: An assembly has at least one integrated circuit (IC) die fixed in a medium. The assembly has a redistribution layer over the IC die. The redistribution layer has conductors connecting first pads on active faces of the IC die to second pads at an exposed surface of the assembly. A die unit is provided over the IC die. The die unit has a bottom die interconnected to a package substrate. Respective portions of the redistribution layer corresponding to each of the at least one IC die partially underlie the bottom die, and extend beyond the bottom die. The package substrate has contacts connected to the ones of the second pads corresponding to the at least one IC die.
    Type: Application
    Filed: October 17, 2013
    Publication date: February 13, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Ding WANG, Chien-Hsun LEE
  • Thin wafer protection device
    Patent number: 8629565
    Abstract: A thin wafer protection device includes a wafer having a plurality of semiconductor chips. The wafer has a first side and an opposite second side. A plurality of dies is over the first side of the wafer, and at least one of the plurality of dies is bonded to at least one of the plurality of semiconductor chips. A wafer carrier is over the second side of the wafer. An encapsulating layer is over the first side of the wafer and the plurality of dies, and the encapsulating layer has a planar top surface. An adhesive tape is over the planar top surface of the encapsulating layer.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ku-Feng Yang, Weng-Jin Wu, Wen-Chih Chiou, Tsung-Ding Wang