Abstract: A laminating structure includes a first magnetic layer, a second magnetic layer, a first spacer disposed between the first and second magnetic layers and a second spacer disposed on the second magnetic layer.

Abstract: A laminating structure includes a first magnetic layer, a second magnetic layer, a first spacer disposed between the first and second magnetic layers and a second spacer disposed on the second magnetic layer.

Abstract: A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact.

Abstract: A method for forming an on-chip magnetic structure includes forming a seed layer over a substrate of a semiconductor chip. The seed layer is patterned to provide a plating location. A cobalt based alloy is electrolessly plated at the plating location to form an inductive structure on the semiconductor chip.

Abstract: A method for forming an on-chip magnetic structure includes forming a seed layer over a substrate of a semiconductor chip. The seed layer is patterned to provide a plating location. A cobalt based alloy is electrolessly plated at the plating location to form an inductive structure on the semiconductor chip.

Abstract: A method for forming a thin film inductor having yokes, one or more of which is laminated, and one or more conductors passing between the yokes. The laminated yoke or yokes help reduce eddy currents and/or hysteresis losses.

Abstract: A thin film inductor having yokes, one or more of which is laminated, and one or more conductors passing between the yokes. The laminated yoke or yokes help reduce eddy currents and/or hysteresis losses.

Abstract: A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.

Abstract: A thin film coupled inductor, a thin film spiral inductor, and a system that includes an electronic device and a power supply or power converter incorporating one or more such inductors. A thin film coupled inductor includes a wafer substrate; a bottom yoke comprising a magnetic material above the wafer substrate; a first insulating layer above the bottom yoke; a first conductor above the bottom yoke and separated therefrom by the first insulating layer; a second insulating layer above the first conductor; a second conductor above the second insulating layer; a third insulating layer above the second conductor; and a non-planar top yoke above the third insulating layer, the top yoke comprising a magnetic material.

Abstract: Processes for selectively patterning a magnetic film structure generally include selectively etching an exposed portion of a freelayer disposed on a tunnel barrier layer by a wet process, which includes exposing the freelayer to an etchant solution comprising at least one acid and an organophosphorus acid inhibitor or salt thereof, stopping on the tunnel barrier layer.

Abstract: Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes forming an opening in a dielectric material layer of a semiconductor device formed above a semiconductor substrate, the opening having sidewalls and a bottom surface. The method also includes forming a first layer of first fill material above the semiconductor device by forming the first layer inside the opening and at least above the sidewalls and the bottom surface of the opening.

Abstract: A thin film inductor having yokes, one or more of which is laminated, and one or more conductors passing between the yokes. The laminated yoke or yokes help reduce eddy currents and/or hysteresis losses.

Abstract: A thin film inductor according to one embodiment includes a bottom yoke; a first insulating layer above the bottom yoke; one or more conductors above the bottom yoke and separated therefrom by the first insulating layer; a second insulating layer above the one or more conductors; a third insulating layer above the second insulating layer; and a top yoke above the third insulating layer. A thin film inductor according to another embodiment includes a bottom yoke; a first insulating layer above the bottom yoke, the first insulating layer being polymeric; one or more conductors above the bottom yoke and separated therefrom by the first insulating layer; an upper insulating layer above the one or more conductors, the upper insulating layer being polymeric; and a top yoke above the second insulating layer.

Abstract: An indium cap layer is formed by blanket depositing indium onto a surface of metallic interconnects separated by interlayer dielectric, and then selectively chemically etching the indium located on the interlayer dielectric leaving an indium cap layer. Etchants containing a strong acid are provided for selectively removing the indium.

Abstract: A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.

Abstract: A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact.

Abstract: Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes forming an opening in a dielectric material layer of a semiconductor device formed above a semiconductor substrate, the opening having sidewalls and a bottom surface. The method also includes forming a first layer of first fill material above the semiconductor device by forming the first layer inside the opening and at least above the sidewalls and the bottom surface of the opening.

Abstract: Processes for selectively patterning a magnetic film structure generally include selectively etching an exposed portion of a freelayer disposed on a tunnel barrier layer by a wet process, which includes exposing the freelayer to an etchant solution comprising at least one acid and an organophosphorus acid inhibitor or salt thereof, stopping on the tunnel barrier layer.

Abstract: Processes for selectively patterning a magnetic film structure generally include selectively etching an exposed portion of a freelayer disposed on a tunnel barrier layer by a wet process, which includes exposing the freelayer to an etchant solution comprising at least one acid and an organophosphorus acid inhibitor or salt thereof, stopping on the tunnel barrier layer.

Abstract: An etching process is employed to selectively pattern an exposed magnetic layer of a magnetic thin film structure. The etching process generally includes selectively patterning a magnetic film structure comprises providing a magnetic structure comprising at least one bottom magnetic layer, at least one top magnetic layer, wherein the at least one bottom magnetic layer is separated from the at least one top magnetic layer by a tunnel barrier layer; and selectively etching the top magnetic layer with an etching solution comprising at least one weakly absorbing acid, a surfactant inhibitor soluble in the at least one weakly absorbing acid, and at least one cation additive, wherein etching of the tunnel barrier layer is substantially prevented. In some embodiments, etching solution comprises at least one perfluoroalkane sulfonic acid, an alkylsulfonate salt soluble in the at least one perfluoroalkane sulfonic acid, and at least one cation additive.