Patents by Inventor Eugene J. O'Sullivan

Eugene J. O'Sullivan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HIGH RESISTIVITY SOFT MAGNETIC MATERIAL FOR MINIATURIZED POWER CONVERTER
    Publication number: 20180076275
    Abstract: An on-chip magnetic structure structure includes a magnetic material comprising cobalt in a range from about 80 to about 90 atomic % (at. %) based on the total number of atoms of the magnetic material, tungsten in a range from about 4 to about 9 at. % based on the total number of atoms of the magnetic material, phosphorous in a range from about 7 to about 15 at. % based on the total number of atoms of the magnetic material, and palladium substantially dispersed throughout the magnetic material.
    Type: Application
    Filed: November 20, 2017
    Publication date: March 15, 2018
    Inventors: Hariklia Deligianni, William J. Gallagher, Andrew J. Kellock, Eugene J. O'Sullivan, Lubomyr T. Romankiw, Naigang Wang
  • MAGNETIC INDUCTOR STACKS WITH MULTILAYER ISOLATION LAYERS
    Publication number: 20180047805
    Abstract: A magnetic laminating structure and process includes alternating layers of a magnetic material and a multilayered insulating material, wherein the multilayered insulating material is intermediate adjacent magnetic material layers and comprises a first insulating layer abutting at least one additional insulating layer, wherein the first insulating layer and the at least one additional insulating layer comprise different dielectric materials and/or are formed by a different deposition process, and wherein the layers of the magnetic material have a cumulative thickness greater than 1 micron.
    Type: Application
    Filed: October 4, 2017
    Publication date: February 15, 2018
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • MAGNETIC INDUCTOR STACKS WITH MULTILAYER ISOLATION LAYERS
    Publication number: 20180019295
    Abstract: A magnetic laminating structure and process includes alternating layers of a magnetic material and a multilayered insulating material, wherein the multilayered insulating material is intermediate adjacent magnetic material layers and comprises a first insulating layer abutting at least one additional insulating layer, wherein the first insulating layer and the at least one additional insulating layer comprise different dielectric materials and/or are formed by a different deposition process, and wherein the layers of the magnetic material have a cumulative thickness greater than 1 micron.
    Type: Application
    Filed: July 14, 2016
    Publication date: January 18, 2018
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • HIGH RESISTIVITY IRON-BASED, THERMALLY STABLE MAGNETIC MATERIAL FOR ON-CHIP INTEGRATED INDUCTORS
    Publication number: 20180012953
    Abstract: An on-chip magnetic structure includes a palladium activated seed layer and a substantially amorphous magnetic material disposed onto the palladium activated seed layer. The substantially amorphous magnetic material includes nickel in a range from about 50 to about 80 atomic % (at. %) based on the total number of atoms of the magnetic material, iron in a range from about 10 to about 50 at. % based on the total number of atoms of the magnetic material, and phosphorous in a range from about 0.1 to about 30 at. % based on the total number of atoms of the magnetic material. The magnetic material can include boron in a range from about 0.1 to about 5 at. % based on the total number of atoms of the magnetic material.
    Type: Application
    Filed: September 7, 2017
    Publication date: January 11, 2018
    Inventors: Hariklia Deligianni, William J. Gallagher, Maurice Mason, Eugene J. O'Sullivan, Lubomyr T. Romankiw, Naigang Wang
  • High resistivity soft magnetic material for miniaturized power converter
    Patent number: 9865673
    Abstract: An on-chip magnetic structure includes a magnetic material comprising cobalt in a range from about 80 to about 90 atomic % (at. %) based on the total number of atoms of the magnetic material, tungsten in a range from about 4 to about 9 at. % based on the total number of atoms of the magnetic material, phosphorous in a range from about 7 to about 15 at. % based on the total number of atoms of the magnetic material, and palladium substantially dispersed throughout the magnetic material.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: January 9, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, William J. Gallagher, Andrew J. Kellock, Eugene J. O'Sullivan, Lubomyr T. Romankiw, Naigang Wang
  • STRESS CONTROL IN MAGNETIC INDUCTOR STACKS
    Publication number: 20180005741
    Abstract: A magnetic laminating structure and process for preventing substrate bowing include a first magnetic layer, at least one additional magnetic layer, and a dielectric spacer disposed between the first and at least one additional magnetic layers. The magnetic layers are characterized by defined tensile strength. To balance the tensile strength of the magnetic layer, the dielectric layer is selected to provide compressive strength so as to counteract the tendency of the wafer to bow as a consequence of the tensile strength imparted by the magnetic layer(s).
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Bruce B. Doris, Hariklia Deligianni, Eugene J. O'Sullivan, Naigang Wang
  • STRESS CONTROL IN MAGNETIC INDUCTOR STACKS
    Publication number: 20180005740
    Abstract: A magnetic laminating structure and process for preventing substrate bowing include multiple film stack segments that include a first magnetic layer, at least one additional magnetic layer, and a dielectric spacer disposed between the first and at least one additional magnetic layers. A dielectric isolation layer is intermediate magnetic layers and on the sidewalls thereof. The magnetic layers are characterized by defined tensile strength and the multiple segments function to relive the stress as the magnetic laminating structure is formed, wherein the cumulative thickness of the magnetic layers is greater than 1 micron. Also described are methods for forming the magnetic laminating structure.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventors: Bruce B. Doris, Hariklia Deligianni, Eugene J. O'Sullivan, Naigang Wang
  • Magnetic inductor stacks with multilayer isolation layers
    Patent number: 9859357
    Abstract: A magnetic laminating structure and process includes alternating layers of a magnetic material and a multilayered insulating material, wherein the multilayered insulating material is intermediate adjacent magnetic material layers and comprises a first insulating layer abutting at least one additional insulating layer, wherein the first insulating layer and the at least one additional insulating layer comprise different dielectric materials and/or are formed by a different deposition process, and wherein the layers of the magnetic material have a cumulative thickness greater than 1 micron.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • High resistivity iron-based, thermally stable magnetic material for on-chip integrated inductors
    Patent number: 9793336
    Abstract: An on-chip magnetic structure includes a palladium activated seed layer and a substantially amorphous magnetic material disposed onto the palladium activated seed layer. The substantially amorphous magnetic material includes nickel in a range from about 50 to about 80 atomic % (at. %) based on the total number of atoms of the magnetic material, iron in a range from about 10 to about 50 at. % based on the total number of atoms of the magnetic material, and phosphorous in a range from about 0.1 to about 30 at. % based on the total number of atoms of the magnetic material. The magnetic material can include boron in a range from about 0.1 to about 5 at. % based on the total number of atoms of the magnetic material.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: October 17, 2017
    Assignee: INTERNATIONAL BUSIENSS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, William J. Gallagher, Maurice Mason, Eugene J. O'Sullivan, Lubomyr T. Romankiw, Naigang Wang
  • LAMINATED STRUCTURES FOR POWER EFFICIENT ON-CHIP MAGNETIC INDUCTORS
    Publication number: 20170294504
    Abstract: Disclosed are magnetic structures, including on-chip inductors comprising laminated layers comprising, in order, a barrier and/or adhesion layer, a antiferromagnetic layer, a magnetic growth layer, a soft magnetic layer, an insulating non-magnetic spacer, a soft magnetic layer, a magnetic growth later, an antiferromagnetic layer. Also disclosed are methods of making such structures.
    Type: Application
    Filed: June 21, 2017
    Publication date: October 12, 2017
    Inventors: Hariklia Deligianni, William J. Gallagher, Eugene J, O'Sullivan, Naigang Wang
  • Laminated structures for power efficient on-chip magnetic inductors
    Patent number: 9761368
    Abstract: Disclosed are magnetic structures, including on-chip inductors comprising laminated layers comprising, in order, a barrier and/or adhesion layer, a antiferromagnetic layer, a magnetic growth layer, a soft magnetic layer, an insulating non-magnetic spacer, a soft magnetic layer, a magnetic growth later, an antiferromagnetic layer. Also disclosed are methods of making such structures.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: September 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, William J. Gallagher, Eugene J. O'Sullivan, Naigang Wang
  • Patterning magnetic films using self-stop electro-etching
    Patent number: 9735224
    Abstract: A method of forming a semiconductor structure includes forming a seed layer over a top surface of a substrate and a protect layer over a top surface of the seed layer. The method also includes forming a magnetic film on a top surface of the protect layer and a top surface of the substrate in at least one opening formed in the seed layer and the protect layer. The method further includes forming at least one patterned magnetic feature on the top surface of the substrate by electro-etching the magnetic film, wherein the seed layer provides a self-stop for the electro-etching of the magnetic film.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventors: Eugene J. O'Sullivan, David L. Rath, Naigang Wang
  • HIGH RESISTIVITY IRON-BASED, THERMALLY STABLE MAGNETIC MATERIAL FOR ON-CHIP INTEGRATED INDUCTORS
    Publication number: 20170229533
    Abstract: An on-chip magnetic structure includes a palladium activated seed layer and a substantially amorphous magnetic material disposed onto the palladium activated seed layer. The substantially amorphous magnetic material includes nickel in a range from about 50 to about 80 atomic % (at. %) based on the total number of atoms of the magnetic material, iron in a range from about 10 to about 50 at. % based on the total number of atoms of the magnetic material, and phosphorous in a range from about 0.1 to about 30 at. % based on the total number of atoms of the magnetic material. The magnetic material can include boron in a range from about 0.1 to about 5 at. % based on the total number of atoms of the magnetic material.
    Type: Application
    Filed: January 20, 2017
    Publication date: August 10, 2017
    Inventors: Hariklia Deligianni, William J. Gallagher, Maurice Mason, Eugene J. O'Sullivan, Lubomyr T. Romankiw, Naigang Wang
  • STRUCTURE AND METHOD TO REDUCE SHORTING AND PROCESS DEGRADATION IN STT-MRAM DEVICES
    Publication number: 20170229641
    Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.
    Type: Application
    Filed: April 27, 2017
    Publication date: August 10, 2017
    Inventors: Anthony J. Annunziata, Gen P. Lauer, Janusz J. Nowak, Eugene J. O'Sullivan
  • MAGNETIC MULTILAYER STRUCTURE
    Publication number: 20170200766
    Abstract: A mechanism is provided for an integrated laminated magnetic device. A substrate and a multilayer stack structure form the device. The multilayer stack structure includes alternating magnetic layers and diode structures formed on the substrate. Each magnetic layer in the multilayer stack structure is separated from another magnetic layer in the multilayer stack structure by a diode structure.
    Type: Application
    Filed: January 25, 2017
    Publication date: July 13, 2017
    Inventors: Philipp Herget, Eugene J. O'Sullivan, Lubomyr T. Romankiw, Naigang Wang, Bucknell C. Webb
  • Structure and method to reduce shorting and process degradation in STT-MRAM devices
    Patent number: 9705071
    Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: July 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Gen P. Lauer, Janusz J. Nowak, Eugene J. O'Sullivan
  • Laminating magnetic cores for on-chip magnetic devices
    Patent number: 9697943
    Abstract: A laminating structure includes a first magnetic layer, a second magnetic layer, a first spacer disposed between the first and second magnetic layers and a second spacer disposed on the second magnetic layer.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: July 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert E. Fontana, Jr., William J. Gallagher, Philipp Herget, Eugene J. O'Sullivan, Lubomyr T. Romankiw, Naigang Wang, Bucknell C. Webb
  • Laminating magnetic cores for on-chip magnetic devices
    Patent number: 9691425
    Abstract: A laminating structure includes a first magnetic layer, a second magnetic layer, a first spacer disposed between the first and second magnetic layers and a second spacer disposed on the second magnetic layer.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: June 27, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert E. Fontana, Jr., William J. Gallagher, Philipp Herget, Eugene J. O'Sullivan, Lubomyr T. Romankiw, Naigang Wang, Bucknell C. Webb
  • LAMINATED STRUCTURES FOR POWER EFFICIENT ON-CHIP MAGNETIC INDUCTORS
    Publication number: 20170178788
    Abstract: Disclosed are magnetic structures, including on-chip inductors comprising laminated layers comprising, in order, a barrier and/or adhesion layer, a antiferromagnetic layer, a magnetic growth layer, a soft magnetic layer, an insulating non-magnetic spacer, a soft magnetic layer, a magnetic growth later, an antiferromagnetic layer. Also disclosed are methods of making such structures.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Inventors: Hariklia Deligianni, William J. Gallagher, Eugene J. O'Sullivan, Naigang Wang
  • STRUCTURE AND METHOD TO REDUCE SHORTING AND PROCESS DEGRADATION IN STT-MRAM DEVICES
    Publication number: 20170148976
    Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.
    Type: Application
    Filed: November 24, 2015
    Publication date: May 25, 2017
    Inventors: Anthony J. Annunziata, Gen P. Lauer, Janusz J. Nowak, Eugene J. O'Sullivan