Patents by Inventor Franz-Josef Niedernostheide
Franz-Josef Niedernostheide has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10249746Abstract: A superjunction bipolar transistor includes an active transistor cell area that includes active transistor cells electrically connected to a first load electrode at a front side of a semiconductor body. A superjunction area overlaps the active transistor cell area and includes a low-resistive region and a reservoir region outside of the low-resistive region. The low-resistive region includes a first superjunction structure with a first vertical extension with respect to a first surface at the front side of the semiconductor body. The reservoir region includes no superjunction structure such that the reservoir region includes the semiconductor body that extends from a region located at the first surface to a drain region.Type: GrantFiled: December 28, 2017Date of Patent: April 2, 2019Assignee: Infineon Technologies AGInventors: Frank Dieter Pfirsch, Franz-Josef Niedernostheide, Hans-Joachim Schulze, Stephan Voss
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Publication number: 20190081142Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, first and second cells electrically connected to the first load terminal structure and to a drift region, the drift region having a first conductivity type; a first mesa in the first cell and including: a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region; a second mesa in the second cell and including: a port region of the opposite conductivity type and electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined, in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure. The insulation structure houses a control electrode structure, and a guidance electrode arranged between the mesas.Type: ApplicationFiled: November 13, 2018Publication date: March 14, 2019Inventors: Anton Mauder, Franz-Josef Niedernostheide, Christian Philipp Sandow
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Patent number: 10224206Abstract: Disclosed is a bipolar semiconductor device, comprising a semiconductor body having a first surface; and a base region of a first doping type and a first emitter region in the semiconductor body, wherein the first emitter region adjoins the first surface and comprises a plurality of first type emitter regions of a second doping type complementary to the first doping type, a plurality of second type emitter regions of the second doping type, a plurality of third type emitter regions of the first doping type, and a recombination region comprising recombination centers, wherein the first type emitter regions and the second type emitter regions extend from the first surface into the semiconductor body, wherein the first type emitter regions have a higher doping concentration and extend deeper into the semiconductor body from the first surface than the second type emitter regions, wherein the third type emitter regions adjoin the first type emitter regions and the second type emitter regions, and wherein the recomType: GrantFiled: June 28, 2017Date of Patent: March 5, 2019Assignee: INFINEON TECHNOLOGIES AGInventors: Roman Baburske, Christian Jaeger, Franz Josef Niedernostheide, Hans-Joachim Schulze, Antonio Vellei
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Patent number: 10177230Abstract: A semiconductor device includes a first semiconductor region including a first semiconductor material and a second semiconductor region adjoining the first semiconductor region, the second semiconductor region including a second semiconductor material different from the first semiconductor material. The semiconductor device further includes at least one of a drift zone and a base zone in the first semiconductor region, and at least one type of deep-level dopant in an emitter region of the second semiconductor region. The at least one type of deep-level dopant has a distance to the valence or conduction band of at least 100 meV.Type: GrantFiled: June 4, 2015Date of Patent: January 8, 2019Assignee: Infineon Technologies AGInventors: Stephan Voss, Franz-Josef Niedernostheide, Hans-Joachim Schulze
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Publication number: 20180366464Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, and first and second cells each configured for controlling a load current and electrically connected to the first load terminal structure and to a drift region. A first mesa in the first cell includes a port region electrically connected to the first load terminal structure, and a first channel region coupled to the drift region. A second mesa included in the second cell includes a port region electrically connected to the first load terminal structure, and a second channel region coupled to the drift region. The mesas are spatially confined in a direction perpendicular to a direction of the load current by an insulation structure, and have a total extension of less than 100 nm in that direction. The first channel region includes an inversion channel. The second channel region includes an accumulation channel.Type: ApplicationFiled: August 29, 2018Publication date: December 20, 2018Inventors: Anton Mauder, Franz-Josef Niedernostheide, Christian Philipp Sandow
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Patent number: 10141404Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, first and second cells electrically connected to the first load terminal structure and to a drift region, the drift region having a first conductivity type; a first mesa in the first cell and including: a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region; a second mesa in the second cell and including: a port region of the opposite conductivity type and electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined, in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure. The insulation structure houses a control electrode structure, and a guidance electrode arranged between the mesas.Type: GrantFiled: June 28, 2017Date of Patent: November 27, 2018Assignee: Infineon Technologies AGInventors: Anton Mauder, Christian Philipp Sandow, Franz-Josef Niedernostheide
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Patent number: 10134835Abstract: A power semiconductor device is disclosed. The device includes a semiconductor body coupled to a first load terminal structure and a second load terminal structure, a first cell and a second cell. A first mesa is included in the first cell, the first mesa including: a first port region and a first channel region. A second mesa included in the second cell, the second mesa including a second port region. A third cell is electrically connected to the second load terminal structure and electrically connected to a drift region. The third cell includes a third mesa comprising: a third port region, a third channel region, and a third control electrode.Type: GrantFiled: June 27, 2017Date of Patent: November 20, 2018Assignee: Infineon Technologies AGInventors: Anton Mauder, Franz-Josef Niedernostheide, Frank Dieter Pfirsch, Christian Philipp Sandow
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Patent number: 10134885Abstract: A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main surface, an active trench at the first main surface extending into the drift region, a gate insulating layer at sidewalls and a bottom side of the active trench, a gate conductive layer in the active trench, a source region in the body region, and adjacent to the active trench, a body trench at the first main surface extending into the drift region, the body trench being adjacent to the body region and to the drift region, an insulating layer at sidewalls and at a bottom side of the body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench, and a conductive layer in the body trench.Type: GrantFiled: May 12, 2017Date of Patent: November 20, 2018Assignee: Infineon Technologies AGInventors: Maria Cotorogea, Frank Wolter, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina-Schmidl
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Patent number: 10109624Abstract: An embodiment of a semiconductor device comprises a transistor cell array in a semiconductor body. The transistor cell array comprises transistor cell units. Each of the transistor cell units comprises a control terminal and first and second load terminals, respectively. The transistor cell units are electrically connected in parallel, and the control terminals of the transistor cells units are electrically connected. A first group of the transistor cell units includes a first threshold voltage. A second group of the transistor cell units includes a second threshold voltage larger than the first threshold voltage. A channel width of a transistor cell unit of the first group is smaller than a channel width of a transistor cell unit of the second group.Type: GrantFiled: April 20, 2017Date of Patent: October 23, 2018Assignee: Infineon Technologies AGInventors: Markus Bina, Franz-Josef Niedernostheide, Alexander Philippou
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Patent number: 10083960Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, and first and second cells each configured for controlling a load current and electrically connected to the first load terminal structure and to a drift region. A first mesa in the first cell includes a port region electrically connected to the first load terminal structure, and a first channel region coupled to the drift region. A second mesa included in the second cell includes a port region electrically connected to the first load terminal structure, and a second channel region coupled to the drift region. The mesas are spatially confined in a direction perpendicular to a direction of the load current by an insulation structure, and have a total extension of less than 100 nm in that direction. The first channel region includes an inversion channel. The second channel region includes an accumulation channel.Type: GrantFiled: June 29, 2017Date of Patent: September 25, 2018Assignee: Infineon Technologies AGInventors: Anton Mauder, Franz-Josef Niedernostheide, Christian Philipp Sandow
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Publication number: 20180269871Abstract: Transistor devices are provided. A transistor device includes a unipolar transistor coupled between a first terminal and a second terminal; and a bipolar transistor coupled in parallel to the unipolar transistor between the first terminal and the second terminal. The bipolar transistor is configured to carry a majority of a current flowing through the transistor device when at least one of the current or a control voltage controlling the unipolar transistor and the bipolar transistor exceeds a predetermined threshold. The bipolar transistor is further configured to have a threshold voltage higher than a threshold voltage of the unipolar transistor, and a difference between the threshold voltage of the bipolar transistor and the threshold voltage of the unipolar transistor is at least 1 V.Type: ApplicationFiled: March 15, 2018Publication date: September 20, 2018Applicant: Infineon Technologies Austria AGInventors: Thomas BASLER, Roman BABURSKE, Johannes Georg LAVEN, Franz-Josef NIEDERNOSTHEIDE, Hans-Joachim SCHULZE
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Publication number: 20180269285Abstract: A transistor device includes a first silicon nanowire array-MOSFET and a second silicon nanowire array-MOSFET integrated with a bulk drift region. The first silicon nanowire array-MOSFET is configured as an n-MOSFET by substantially only accommodating an electron current, and the second silicon nanowire array-MOSFET is configured as a p-MOSFET by substantially only accommodating a hole electron current. A current strength of a current through the first silicon nanowire array-MOSFET caused by electrons is at least 10 times larger than a current through the first silicon nanowire array-MOSFET caused by holes in an on-state of the transistor device. Further embodiments of transistor devices are described.Type: ApplicationFiled: May 14, 2018Publication date: September 20, 2018Inventors: Christian Philipp Sandow, Franz Josef Niedernostheide, Vera van Treek
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Publication number: 20180269872Abstract: Transistor devices are described that include a first transistor and a second transistor coupled in parallel between a first terminal and a second terminal. The second transistor is based on a wide bandgap semiconductor material. The second transistor has a breakthrough voltage lower than a breakthrough voltage of the first transistor over a predetermined operating range. The predetermined operating range comprises at least an operating range for which the transistor device is specified.Type: ApplicationFiled: March 15, 2018Publication date: September 20, 2018Applicant: Infineon Technologies AGInventors: Thomas BASLER, Roman BABURSKE, Johannes Georg LAVEN, Franz-Josef NIEDERNOSTHEIDE, Hans-Joachim SCHULZE
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Patent number: 10069016Abstract: A semiconductor diode includes a semiconductor body and trench structures extending from a surface of the semiconductor body into the semiconductor body. The semiconductor body includes a doped layer of a first conductivity type and a doped zone of a second conductivity type opposite to the first conductivity type. The doped zone is formed between the doped layer and a first surface of the semiconductor body. The trench structures are arranged between electrically connected portions of the semiconductor body. The trench structures do not include conductive structures that are both electrically insulated from the semiconductor body and electrically connected with another structure outside the trench structures.Type: GrantFiled: November 20, 2014Date of Patent: September 4, 2018Assignee: Infineon Technologies Austria AGInventors: Anton Mauder, Franz-Josef Niedernostheide, Hans-Joachim Schulze, Holger Schulze
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Patent number: 9997517Abstract: A power semiconductor device is disclosed. In one example, the device includes a semiconductor body coupled to a first load terminal structure and a second load terminal structure. An active cell field is implemented in the semiconductor body. The active cell field is surrounded by an edge termination zone. A plurality of first cells and a plurality of second cells are provided in the active cell field. Each first cell includes a first mesa, the first mesa including: a first port region and a first channel region. Each second cell includes a second mesa, the second mesa including a second port region. The active cell field is surrounded by a drainage region that is arranged between the active cell field and the edge termination zone.Type: GrantFiled: June 28, 2017Date of Patent: June 12, 2018Assignee: Infineon Technologies AGInventors: Anton Mauder, Franz-Josef Niedernostheide, Christian Philipp Sandow
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Publication number: 20180158937Abstract: A superjunction bipolar transistor includes an active transistor cell area that includes active transistor cells electrically connected to a first load electrode at a front side of a semiconductor body. A superjunction area overlaps the active transistor cell area and includes a low-resistive region and a reservoir region outside of the low-resistive region. The low-resistive region includes a first superjunction structure with a first vertical extension with respect to a first surface at the front side of the semiconductor body. The reservoir region includes no superjunction structure such that the reservoir region includes the semiconductor body that extends from a region located at the first surface to a drain region.Type: ApplicationFiled: December 28, 2017Publication date: June 7, 2018Applicant: Infineon Technologies AGInventors: Frank Dieter PFIRSCH, Franz-Josef NIEDERNOSTHEIDE, Hans-Joachim SCHULZE, Stephan VOSS
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Patent number: 9978837Abstract: An insulated gate bipolar transistor device includes a semiconductor substrate having a drift region of an insulated gate bipolar transistor structure, a first fin structure starting from the drift region of the semiconductor substrate and extending orthogonal to a main surface of the semiconductor substrate, and a first gate structure of the insulated gate bipolar transistor structure extending alma at least a part of the first fin structure.Type: GrantFiled: December 6, 2016Date of Patent: May 22, 2018Assignee: Infineon Technologies AGInventors: Christian Philipp Sandow, Franz Josef Niedernostheide, Vera van Treek
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Publication number: 20180138301Abstract: A power semiconductor transistor includes a trench extending into a semiconductor body along a vertical direction and having first and second trench sidewalls and a trench bottom, an electrode in the trench electrically insulated from the semiconductor body, drift and source regions of a first conductivity type, a semiconductor channel region of a second conductivity type laterally adjacent the first trench sidewall and separating the source and drift regions, and a guidance zone. The guidance zone includes a bar section of the second conductivity type extending along the second trench sidewall or along a sidewall of another trench in the vertical direction to a depth in the semiconductor body deeper than the trench bottom, and a plateau section of the second conductivity type adjoining the bar section and extending under the trench bottom towards the semiconductor channel region. The plateau section has at least one opening below the channel region.Type: ApplicationFiled: December 26, 2017Publication date: May 17, 2018Inventors: Anton Mauder, Franz-Josef Niedernostheide, Christian Philipp Sandow
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Patent number: 9947741Abstract: In a field-effect semiconductor device, alternating first n-type and p-type pillar regions are arranged in the active area. The first n-type pillar regions are in Ohmic contact with the drain metallization. The first p-type pillar regions are in Ohmic contact with the source metallization. An integrated dopant concentration of the first n-type pillar regions substantially matches that of the first p-type pillar regions. A second p-type pillar region is in Ohmic contact with the source metallization, arranged in the peripheral area and has an integrated dopant concentration smaller than that of the first p-type pillar regions divided by a number of the first p-type pillar regions. A second n-type pillar region is arranged between the second p-type pillar region and the first p-type pillar regions, and has an integrated dopant concentration smaller than that of the first n-type pillar regions divided by a number of the first n-type pillar regions.Type: GrantFiled: February 3, 2017Date of Patent: April 17, 2018Assignee: Infineon Technologies Austria AGInventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Anton Mauder, Joachim Weyers, Franz Hirler, Markus Schmitt, Armin Willmeroth, Björn Fischer, Stefan Gamerith
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Patent number: 9917181Abstract: A superjunction bipolar transistor includes an active transistor cell area that includes active transistor cells electrically connected to a first load electrode at a front side of a semiconductor body. A superjunction area overlaps the active transistor cell area and includes a low-resistive region and a reservoir region outside of the low-resistive region. The low-resistive region includes a first superjunction structure with a first vertical extension with respect to a first surface of the semiconductor body. The reservoir region includes no superjunction structure or a second superjunction structure with a mean second vertical extension smaller than the first vertical extension.Type: GrantFiled: October 18, 2016Date of Patent: March 13, 2018Assignee: Infineon Technologies AGInventors: Frank Dieter Pfirsch, Franz-Josef Niedernostheide, Hans-Joachim Schulze, Stephan Voss