Patents by Inventor Franz-Josef Niedernostheide

Franz-Josef Niedernostheide has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170148872
    Abstract: In a field-effect semiconductor device, alternating first n-type and p-type pillar regions are arranged in the active area. The first n-type pillar regions are in Ohmic contact with the drain metallization. The first p-type pillar regions are in Ohmic contact with the source metallization. An integrated dopant concentration of the first n-type pillar regions substantially matches that of the first p-type pillar regions. A second p-type pillar region is in Ohmic contact with the source metallization, arranged in the peripheral area and has an integrated dopant concentration smaller than that of the first p-type pillar regions divided by a number of the first p-type pillar regions. A second n-type pillar region is arranged between the second p-type pillar region and the first p-type pillar regions, and has an integrated dopant concentration smaller than that of the first n-type pillar regions divided by a number of the first n-type pillar regions.
    Type: Application
    Filed: February 3, 2017
    Publication date: May 25, 2017
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Anton Mauder, Joachim Weyers, Franz Hirler, Markus Schmitt, Armin Willmeroth, Björn Fischer, Stefan Gamerith
  • Publication number: 20170140938
    Abstract: A method of forming a semiconductor device includes irradiating a semiconductor body with particles. Dopant ions are implanted into the semiconductor body such that the dopant ions are configured to be activated as donors or acceptors. Thereafter, the semiconductor body is processed thermally.
    Type: Application
    Filed: November 10, 2016
    Publication date: May 18, 2017
    Applicant: Infineon Technologies AG
    Inventors: Franz-Josef NIEDERNOSTHEIDE, Johannes Georg LAVEN, Hans-Joachim SCHULZE
  • Patent number: 9647100
    Abstract: A semiconductor device includes transistor cells formed along a first surface at a front side of a semiconductor body in a transistor cell area. A drift zone structure forms first pn junctions with body zones of the transistor cells. An auxiliary structure between the drift zone structure and a second surface at a rear side of the semiconductor body includes a first portion that contains deep level dopants requiring at least 150 meV to ionize. A collector structure directly adjoins the auxiliary structure. An injection efficiency of minority carriers from the collector structure into the drift zone structure varies along a direction parallel to the first surface at least in the transistor cell area.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: May 9, 2017
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Christian Jaeger, Franz Josef Niedernostheide, Roman Baburske, Andre Rainer Stegner, Antonio Vellei
  • Publication number: 20170125407
    Abstract: A semiconductor device and a method for producing thereof is provided. The semiconductor device includes a plurality of device cells, each comprising a body region, a source region, and a gate electrode adjacent to the body region and dielectrically insulated from the body region by a gate dielectric; and an electrically conductive gate layer comprising the gate electrodes or electrically connected to the gate electrodes of the plurality of device cells. The gate layer is electrically connected to a gate conductor and includes at least one of an increased resistance region and a decreased resistance region.
    Type: Application
    Filed: October 21, 2016
    Publication date: May 4, 2017
    Applicant: Infineon Technologies AG
    Inventors: Hans-Joachim SCHULZE, Franz-Josef NIEDERNOSTHEIDE, Frank Dieter PFIRSCH, Francisco Javier SANTOS RODRIGUEZ, Stephan VOSS, Wolfgang WAGNER
  • Publication number: 20170117394
    Abstract: A superjunction bipolar transistor includes an active transistor cell area that includes active transistor cells electrically connected to a first load electrode at a front side of a semiconductor body. A superjunction area overlaps the active transistor cell area and includes a low-resistive region and a reservoir region outside of the low-resistive region. The low-resistive region includes a first superjunction structure with a first vertical extension with respect to a first surface of the semiconductor body. The reservoir region includes no superjunction structure or a second superjunction structure with a mean second vertical extension smaller than the first vertical extension.
    Type: Application
    Filed: October 18, 2016
    Publication date: April 27, 2017
    Applicant: Infineon Technologies AG
    Inventors: Frank Dieter PFIRSCH, Franz-Josef NIEDERNOSTHEIDE, Hans-Joachim SCHULZE, Stephan VOSS
  • Publication number: 20170117397
    Abstract: A power semiconductor transistor includes a semiconductor body coupled to a load terminal, a drift region, a first trench extending into the semiconductor body and including a control electrode electrically insulated from the semiconductor body by an insulator, a source region arranged laterally adjacent to a sidewall of the first trench and electrically connected to the load terminal, a channel region arranged laterally adjacent to the same trench sidewall as the source region, a second trench extending into the semiconductor body, and a guidance zone electrically connected to the load terminal and extending deeper into the semiconductor body than the first trench. The guidance zone is adjacent the opposite sidewall of the first trench as the source region and adjacent one sidewall of the second trench. In a section arranged deeper than the bottom of the first trench, the guidance zone extends laterally towards the channel region.
    Type: Application
    Filed: October 21, 2016
    Publication date: April 27, 2017
    Inventors: Anton Mauder, Franz-Josef Niedernostheide, Christian Philipp Sandow
  • Patent number: 9627517
    Abstract: A bipolar semiconductor switch having a semiconductor body is provided. The semiconductor body includes a first p-type semiconductor region, a second p-type semiconductor region, and a first n-type semiconductor region forming a first pn-junction with the first p-type semiconductor region and a second pn-junction with the second p-type semiconductor region. On a shortest path through the first n-type semiconductor region between the first pn-junction and the second pn-junction a concentration of charge recombination centers and a concentration of n-dopants vary. The concentration of the charge recombination centers has a maximum at a point along the shortest path where the concentration of n-dopants is at least close to a maximum dopant concentration. Further, a manufacturing method for the bipolar semiconductor switch is provided.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: April 18, 2017
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide
  • Publication number: 20170084692
    Abstract: An insulated gate bipolar transistor device includes a semiconductor substrate having a drift region of an insulated gate bipolar transistor structure, a first fin structure starting from the drift region of the semiconductor substrate and extending orthogonal to a main surface of the semiconductor substrate, and a first gate structure of the insulated gate bipolar transistor structure extending alma at least a part of the first fin structure.
    Type: Application
    Filed: December 6, 2016
    Publication date: March 23, 2017
    Inventors: Christian Philipp Sandow, Franz Josef Niedernostheide, Vera van Treek
  • Patent number: 9570607
    Abstract: In a field-effect semiconductor device, alternating first n-type and p-type pillar regions are arranged in the active area. The first n-type pillar regions are in Ohmic contact with the drain metallization. The first p-type pillar regions are in Ohmic contact with the source metallization. An integrated dopant concentration of the first n-type pillar regions substantially matches that of the first p-type pillar regions. A second p-type pillar region is in Ohmic contact with the source metallization, arranged in the peripheral area and has an integrated dopant concentration smaller than that of the first p-type pillar regions divided by a number of the first p-type pillar regions. A second n-type pillar region is arranged between the second p-type pillar region and the first p-type pillar regions, and has an integrated dopant concentration smaller than that of the first n-type pillar regions divided by a number of the first n-type pillar regions.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: February 14, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Anton Mauder, Joachim Weyers, Franz Hirler, Markus Schmitt, Armin Willmeroth, Björn Fischer, Stefan Gamerith
  • Publication number: 20170033794
    Abstract: A semiconductor device includes a first transistor cell of a plurality of transistor cells of a vertical field effect transistor arrangement, and a second transistor cell of the plurality of transistor cells. The first transistor cell and the second transistor cell are electrically connected in parallel. A gate of the first transistor cell and a gate of the second transistor cell are controllable by different gate control signals.
    Type: Application
    Filed: July 29, 2016
    Publication date: February 2, 2017
    Inventors: Christian Philipp Sandow, Franz-Josef Niedernostheide
  • Publication number: 20170025408
    Abstract: A semiconductor device comprising a source region being electrically connected to a first load terminal (E) of the semiconductor device and a drift region comprising a first semiconductor material (M1) having a first band gap, the drift region having dopants of a first conductivity type and being configured to carry at least a part of a load current between the first load terminal (E) and a second load terminal (C) of the semiconductor device, is presented. The semiconductor device further comprises a semiconductor body region having dopants of a second conductivity type complementary to the first conductivity type and being electrically connected to the first load terminal (E), a transition between the semiconductor body region and the drift region forming a pn-junction, wherein the pn-junction is configured to block a voltage applied between the first load terminal (E) and the second load terminal (C).
    Type: Application
    Filed: July 14, 2016
    Publication date: January 26, 2017
    Inventors: Hans-Joachim Schulze, Holger Huesken, Franz-Josef Niedernostheide, Frank Dieter Pfirsch, Roman Roth, Christian Philipp Sandow, Carsten Schaeffer, Stephan Voss
  • Patent number: 9536740
    Abstract: A description is given of a method for doping a semiconductor body, and a semiconductor body produced by such a method. The method comprises irradiating the semiconductor body with protons and irradiating the semiconductor body with electrons. After the process of irradiating with protons and after the process of irradiating with electrons, the semiconductor body is subjected to heat treatment in order to attach the protons to vacancies by means of diffusion.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: January 3, 2017
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Johannes Laven, Franz Josef Niedernostheide, Frank Dieter Pfirsch
  • Patent number: 9525029
    Abstract: An insulated gate bipolar transistor device includes a semiconductor substrate having a drift region of an insulated gate bipolar transistor structure. Further, the insulated gate bipolar transistor device includes a first nanowire structure and a first gate structure. The first nanowire structure of the insulated gate bipolar transistor structure is connected to the drift region, and the first gate structure of the insulated gate bipolar transistor structure extends along at least a part of the first nanowire structure.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: December 20, 2016
    Assignee: Infineon Technologies AG
    Inventors: Christian Philipp Sandow, Franz Josef Niedernostheide, Vera van Treek
  • Publication number: 20160284803
    Abstract: Disclosed is a bipolar semiconductor device, comprising a semiconductor body having a first surface; and a base region of a first doping type and a first emitter region in the semiconductor body, wherein the first emitter region adjoins the first surface and comprises a plurality of first type emitter regions of a second doping type complementary to the first doping type, a plurality of second type emitter regions of the second doping type, a plurality of third type emitter regions of the first doping type, and a recombination region comprising recombination centers, wherein the first type emitter regions and the second type emitter regions extend from the first surface into the semiconductor body, wherein the first type emitter regions have a higher doping concentration and extend deeper into the semiconductor body from the first surface than the second type emitter regions, wherein the third type emitter regions adjoin the first type emitter regions and the second type emitter regions, and wherein the recom
    Type: Application
    Filed: March 25, 2016
    Publication date: September 29, 2016
    Inventors: Roman Baburske, Christian Jaeger, Franz Josef Niedernostheide, Hans-Joachim Schulze, Antonio Vellei
  • Patent number: 9412824
    Abstract: A semiconductor component includes a semiconductor body having a first side and a second side opposite the first side. In the semiconductor body, a dopant region is formed by a dopant composed of an oxygen complex. The dopant region extends over a section L having a length of at least 10 ?m along a direction from the first side to the second side. The dopant region has an oxygen concentration in a range of 1×1017 cm?3 to 5×1017 cm?3 over the section L.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: August 9, 2016
    Assignee: Infineon Technologies AG
    Inventors: Thomas Neidhart, Franz Josef Niedernostheide, Hans-Joachim Schulze, Werner Schustereder, Alexander Susiti
  • Patent number: 9412854
    Abstract: An IGBT module is provided. The IGBT module has at least a first individual IGBT with a first softness during switching-off the IGBT module, and at least a second individual IGBT connected in parallel to the at least one first IGBT. The at least one second individual IGBT has a second softness during switching-off the IGBT module which is different than the first softness. Further a circuit and an electronic power device having two individual IGBTs, which are connected in parallel, are provided.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: August 9, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Peter Felsl, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Thomas Raker
  • Patent number: 9373710
    Abstract: A semiconductor component is described herein. In accordance with one example of the invention, the semiconductor component includes a semiconductor body, which has a top surface and a bottom surface. A body region, which is doped with dopants of a second doping type, is arranged at the top surface of the semiconductor body. A drift region is arranged under the body region and doped with dopants of a first doping type, which is complementary to the second doping type. Thus a first pn-junction is formed at the transition between the body region and the drift region. A field stop region is arranged under the drift region and adjoins the drift region. The field stop region is doped with dopants of the same doping type as the drift region. However, the concentration of dopants in the field stop region is higher than the concentration of dopants in the drift region. At least one pair of semiconductor layers composed of a first and a second semiconductor layer are arranged in the drift region.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: June 21, 2016
    Assignee: Infineon Technologies AG
    Inventors: Vera Van Treek, Frank Pfirsch, Roman Baburske, Franz-Josef Niedernostheide
  • Publication number: 20160155735
    Abstract: A semiconductor component including a short-circuit structure. One embodiment provides a semiconductor component having a semiconductor body composed of doped semiconductor material. The semiconductor body includes a first zone of a first conduction type and a second zone of a second conduction type, complementary to the first conduction type, the second zone adjoining the first zone. The first zone and the second zone are coupled to an electrically highly conductive layer. A connection zone of the second conduction type is arranged between the second zone and the electrically highly conductive layer.
    Type: Application
    Filed: February 5, 2016
    Publication date: June 2, 2016
    Applicant: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Uwe Kellner-Werdehausen, Reiner Barthelmess
  • Publication number: 20160111528
    Abstract: A semiconductor device includes transistor cells formed along a first surface at a front side of a semiconductor body in a transistor cell area. A drift zone structure forms first pn junctions with body zones of the transistor cells. An auxiliary structure between the drift zone structure and a second surface at a rear side of the semiconductor body includes a first portion that contains deep level dopants requiring at least 150 meV to ionize. A collector structure directly adjoins the auxiliary structure. An injection efficiency of minority carriers from the collector structure into the drift zone structure varies along a direction parallel to the first surface at least in the transistor cell area.
    Type: Application
    Filed: October 20, 2015
    Publication date: April 21, 2016
    Inventors: Hans-Joachim Schulze, Christian Jaege, Franz Josef Niedernostheide, Roman Baburske, Andre Rainer Stegner, Antonio Vellei
  • Publication number: 20160064554
    Abstract: In a field-effect semiconductor device, alternating first n-type and p-type pillar regions are arranged in the active area. The first n-type pillar regions are in Ohmic contact with the drain metallization. The first p-type pillar regions are in Ohmic contact with the source metallization. An integrated dopant concentration of the first n-type pillar regions substantially matches that of the first p-type pillar regions. A second p-type pillar region is in Ohmic contact with the source metallization, arranged in the peripheral area and has an integrated dopant concentration smaller than that of the first p-type pillar regions divided by a number of the first p-type pillar regions. A second n-type pillar region is arranged between the second p-type pillar region and the first p-type pillar regions, and has an integrated dopant concentration smaller than that of the first n-type pillar regions divided by a number of the first n-type pillar regions.
    Type: Application
    Filed: November 6, 2015
    Publication date: March 3, 2016
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Anton Mauder, Joachim Weyers, Franz Hirler, Markus Schmitt, Armin Willmeroth, Björn Fischer, Stefan Gamerith