Abstract: An inverter-based comparator, powered between a first supply voltage and a second supply voltage being lower than the first supply voltage, includes a first inverter branch composed of at least one first P-type transistor and at least one first N-type transistor; and a second inverter branch composed of at least one second P-type transistor, at least one second N-type transistor and at least two tuning switches. The first inverter branch and the second inverter branch are configured to compare an input voltage with an internal trigger point, thereby generating a compare voltage at an interconnected node. One of the at least two tuning switches is controlled to isolate the first supply voltage and another is controlled to isolate the second supply voltage to compensate for trigger point shifting.

Abstract: The present disclosure provides a scan driving circuit, which includes a pull-up output charging circuit, a pull-down discharge circuit, a pre-charge circuit, an anti-noise start-up circuit and an anti-noise pull-down discharge circuit. The pull-up output charging circuit is electrically connected to an output terminal, and the pull-down discharge circuit is electrically connected to the output terminal. The pre-charge circuit is electrically connected to the pull-up output charging circuit and the pull-down discharge circuit through a driving node. The anti-noise start-up circuit is electrically connected to the pre-charge circuit. The anti-noise pull-down discharge circuit is electrically connected to the anti-noise start-up circuit, and the anti-noise pull-down discharge circuit is electrically connected to the driving node.

Abstract: A socket includes a first section and a second section. The first section is to be connected with a tool. The second section includes an outer face, and a mounting hole is axially defined through the second section and communicates through the first section. The mounting hole includes multiple recesses and multiple sides defined in the inner periphery thereof. The multiple recesses and the multiple sides are located alternatively with each other. Each recess includes a rounded corner formed radially in the inner portion thereof. A triangular groove is formed axially and centrally in each side. The angle between two insides of each groove is smaller than 90 degrees. A rusted or damaged bolt head is engaged with either the rounded corners or the grooves so as to be effectively rotated.

Abstract: A syringe stabilizing apparatus has a base and a syringe support. The syringe support is vertically disposed above the base, elevating a fluid-filled portion of an infusion set vertically above the base and orienting a delivery end of the fluid-filled portion upwardly relative to a horizontal plane to take advantage of a gravitational effect on a fluid during delivery of the fluid from the fluid-filled portion to a patient. The syringe support comprises a first retainer and a selectively actuated tube clamp. The first retainer has an opening in which a rigid portion of the infusion set is received and retained therein without further user intervention. The selectively actuated tube clamp is operatively aligned with the first retainer wherein a flexible tube extending from the rigid portion of the infusion set extends through the tube clamp.

Abstract: A method of making a semiconductor device includes implanting a source/drain (S/D) in the substrate adjacent to a gate structure. The method further includes implanting a lightly doped drain (LDD) region in the substrate in direct contact with the S/D, wherein a dopant concentration in the LDD region is less than a dopant concentration in the S/D. The method further includes implanting a doping extension region in the substrate in direct contact with the LDD region, wherein a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.

Abstract: A ratchet ring includes six first driving portions formed to the inner periphery of the ratchet ring. Each first driving portion includes a first driving face and a toothed face. A second driving portion is formed in each of the six first driving portions and includes two second driving faces which respectively extend from the first driving face and the toothed face. A first angle is formed between the two second driving faces. A third driving portion is formed in each of the six first driving portions and includes a recess located between the two second driving faces. A second angle is formed between two sides of the recess. A step is formed between the two second driving faces and the third driving portion. When a corner of an object is engaged between the two second driving faces, the step avoids the object from dropping from the ratchet ring.

Abstract: A memory device and programming method thereof are provided. A memory cell array includes a first dummy word line set, plural word lines and a second dummy word line set in sequence. The method includes: grouping the word lines into word line groups; generating at least one pass bias set having plural pass biases that are respectively corresponding to each word line group; selecting one word line for programming, and determining that the selected word line belongs to a specific word line group; and according to a programming sequence, applying a corresponding pass bias in the plural pass biases of the at least one pass bias set to at least one dummy word line in one of the first and the second dummy word line sets, wherein the corresponding pass bias corresponds to the specific word line group.

Abstract: In a method of manufacturing a semiconductor device, a sacrificial gate structure including sacrificial gate electrode is formed over a substrate. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. The recessing the first dielectric layer comprises a first etching operation and a second etching operation using a different etching as from the first etching operation.

Abstract: A nitride-based semiconductor device includes a buffer, a first nitride-based semiconductor layer, a shield layer, a second nitride-based semiconductor layer, a pair of S/D electrodes, and a gate electrode. The first nitride-based semiconductor layer is disposed over the buffer and forms a first interface with the buffer. The shield layer includes a first isolation compound and is interposed between the buffer and the first nitride-based semiconductor layer. The first isolation compound has a bandgap greater than a bandgap of the buffer and greater than a bandgap of the first nitride-based semiconductor layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap less than the bandgap of the first isolation compound and greater than the bandgap of the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.

Abstract: A method includes: providing a substrate defining a scribe line region and a device region adjacent to the scribe line region; depositing a first mask layer over the device region and the scribe line region; patterning the first mask layer to define a plurality of first areas in the device region and a plurality of second areas in the scribe line region, wherein the first areas and the second areas are parallel and extending in a first direction from a top-view perspective; performing a first ion implantation to form first well regions in the first areas and second well regions in the second areas; coupling conductive pads to the second well regions; and performing a test on the second well regions through the conductive pads.

Abstract: A bonding method and a bonding structure are provided. A device substrate is provided including a plurality of semiconductor devices, wherein each of the semiconductor devices includes a first bonding layer. A cap substrate is provided including a plurality of cap structures, wherein each of the cap structures includes a second bonding layer, the second bonding layer having a planar surface and a first protrusion protruding from the planar surface. The device substrate is bonded to the cap substrate by engaging the first protrusion of the second bonding layer of each of the cap structures with the corresponding first bonding layer of each of the semiconductor devices in the device substrate.

Abstract: A wrench includes a handle and a working end, two arms extend from the working end to form a room between the two arms. Each arm includes a locking hole. A driving head is pivotably connected between the two arms. Two bolts are respectively and threadedly connected to the locking holes of the two arms, and inserted into the two recesses of the driving head to pivotably position the driving head. A wave washer is mounted to each of the two bolts and sandwiched between the driving head and the arm. The convex portions one side of each wave washer contact the outside of the driving head. The convex portions on other side of each wave washer contact the inside of the arm corresponding thereto. The friction between the driving head and the arms is reduced when the driving head is pivoted relative to the arms.

Abstract: This disclosure relates to a polishing composition that includes an abrasive, at least two pH adjusters, a barrier film removal rate enhancer, a low-k removal rate inhibitor, and an azole-containing corrosion inhibitor. This disclosure also features a method of using the polishing composition to polish a substrate containing copper and silicon oxide.

Abstract: A layout includes a first and a second standard cells abutting along a boundary line. The first cell includes first fins. An edge of the first fins closest to and away from the boundary line by a distance D1. A first gate line over-crossing the first fins protrudes from the edge by a length L1. The second cell includes second fins. An edge of the second fins closest to and away from the boundary line by a distance D2. A second gate line over-crossing the second fins protrudes from the edge by a length L2. Two first dummy gate lines at two sides of the first fins and two second dummy lines at two sides of the second fins are respectively away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1?D1?S, L2?D2?S, and D1?D2.

Abstract: A hand tool with angle adjusting mechanism includes a handle, a driving head, an engaging assembly and a button. The handle has a receiving groove, a transverse hole and a longitudinal hole. The driving head has a connecting portion disposed in the receiving groove. The engaging assembly has an engaging member and a spring. The engaging member has an engaging tooth at a top thereof for engagement with the driving head, and has an arc-shape pushing groove in a lateral side with an arc-shape wall inside thereof. The button is movably disposed in the transverse hole of the handle, and has an abutting portion slidably inserted in the arc-shape pushing groove, the abutting portion of the button has an arc-shape plane abutting against the arc-shape wall such that horizontal movement of the button drives the engaging member to move longitudinally along the longitudinal hole of the handle.

Abstract: The present disclosure provides a pixel circuit with pulse width compensation, and the pixel circuit includes a pulse width modulation circuit and a pulse amplitude modulation circuit, and the pulse amplitude modulation circuit is electrically connected to the pulse width modulation circuit. The pulse width modulation circuit includes a P-type pulse width compensation transistor and a first P-type control transistor, and the first P-type control transistor is electrically connected to the P-type pulse width compensation transistor. The pulse amplitude modulation circuit includes a second P-type control transistor, a first capacitor, a P-type driving transistor and a light-emitting element. The second P-type control transistor is electrically connected to the first P-type control transistor. The first capacitor is electrically connected to the second P-type control transistor.

Abstract: The present disclosure provides a scan driving circuit, which includes a pull-up output charging circuit, a pull-down discharge circuit, a pre-charge circuit, an anti-noise start-up circuit and an anti-noise pull-down discharge circuit. The pull-up output charging circuit is electrically connected to an output terminal, and the pull-down discharge circuit is electrically connected to the output terminal. The pre-charge circuit is electrically connected to the pull-up output charging circuit and the pull-down discharge circuit through a driving node. The anti-noise start-up circuit is electrically connected to the pre-charge circuit. The anti-noise pull-down discharge circuit is electrically connected to the anti-noise start-up circuit, and the anti-noise pull-down discharge circuit is electrically connected to the driving node.

Abstract: The present disclosure provides a scan driving circuit, which includes a pull-up output charging circuit, a pull-down discharge circuit, a pre-charge circuit, an anti-noise start-up circuit and an anti-noise pull-down discharge circuit. The pull-up output charging circuit is electrically connected to an output terminal, and the pull-down discharge circuit is electrically connected to the output terminal. The pre-charge circuit is electrically connected to the pull-up output charging circuit and the pull-down discharge circuit through a driving node. The anti-noise start-up circuit is electrically connected to the pre-charge circuit. The anti-noise pull-down discharge circuit is electrically connected to the anti-noise start-up circuit, and the anti-noise pull-down discharge circuit is electrically connected to the driving node.

Abstract: A syringe stabilizing apparatus has a base and a syringe support. The syringe support is vertically disposed above the base, elevating a fluid-filled portion of an infusion set vertically above the base and orienting a delivery end of the fluid-filled portion upwardly relative to a horizontal plane to take advantage of a gravitational effect on a fluid during delivery of the fluid from the fluid-filled portion to a patient. The syringe support comprises a first retainer and a selectively actuated tube clamp. The first retainer has an opening in which a rigid portion of the infusion set is received and retained therein without further user intervention. The selectively actuated tube clamp is operatively aligned with the first retainer. A flexible tube extending from the rigid portion of the infusion set extends through the selectively actuated tube clamp.

Abstract: A semiconductor device includes a substrate, a bottom electrode, a ferroelectric layer, a noble metal electrode, and a non-noble metal electrode. The bottom electrode is over the substrate. The ferroelectric layer is over the bottom electrode. The noble metal electrode is over the ferroelectric layer. The non-noble metal electrode is over the noble metal electrode.