Abstract: An integrated nucleic acid loop-mediated isothermal amplification and mobile device system is provided and includes a main body and a power supply, where the 5 main body at least has a delivery unit, a heating unit and a control unit, the control unit is electrically connected to the delivery unit and the heating unit, and the power supply is electrically connected to the main body. A method for operating the integrated nucleic acid loop-mediated isothermal amplification and mobile device system is also provided.

Abstract: A heat exchange system having desired anti-scaling performance and an anti-scaling method thereof are disclosed. The heat exchange system at least comprises a load control unit, a temperature and pressure detection unit and an anti-scaling treatment unit. The heat exchange system conditions bonding ways of water quality in a HVAC chiller unit, an air compressor, a heat exchanger, a cooling unit, or a boiler under a variety of scaling conditions in both field operation and water quality, by integrating the interaction of those units together with the anti-scaling method for simulating water quality that has a water quality limit same as that in field operation. The heat exchange system further integrates with a testing of anti-scaling performance to make water quality no longer charged and lose the reaction power so as to prevent scaling formation, enhance the anti-scaling performance, and ensure operating efficiency and performance.

Abstract: A semiconductor device includes a bottom electrode, a top electrode, a sidewall spacer, and a data storage element. The sidewall spacer is disposed aside the top electrode. The data storage element is located between the bottom electrode and the top electrode, and includes a ferroelectric material. The data storage element has a peripheral region which is disposed beneath the sidewall spacer and which has at least 60% of ferroelectric phase. A method for manufacturing the semiconductor device and a method for transforming a non-ferroelectric phase of a ferroelectric material to a ferroelectric phase are also disclosed.

Abstract: A card edge connector includes: an insulating housing defining a card slot opening forwards through a front face thereof; plural terminals retained in the insulating housing and including contacting portions extending into the card slot and soldering portions exposed upon a bottom face of the housing; and a metal shell at least partially covering the insulating housing, wherein the metal shell including a flat plate and a pair of side plates bending downwards from the flat plate, and the flat plate is at least partially embedded in the insulating housing and located proximate to a top face.

Abstract: A bonding method and a bonding structure are provided. A device substrate is provided including a plurality of semiconductor devices, wherein each of the semiconductor devices includes a first bonding layer. A cap substrate is provided including a plurality of cap structures, wherein each of the cap structures includes a second bonding layer, the second bonding layer having a planar surface and a first protrusion protruding from the planar surface. The device substrate is bonded to the cap substrate by engaging the first protrusion of the second bonding layer of each of the cap structures with the corresponding first bonding layer of each of the semiconductor devices in the device substrate.

Abstract: The present invention provides a battery probing module, for testing a battery defined with a contact surface having a first electrode area and a second electrode area with different polarities. The battery probing module comprises a frame and a plurality of probe units. The frame has a top plate and a bottom plate opposite to the top plate. Each of the plurality of probe units comprises a base, a first probe, and a plurality of second probes. The base is defined with a top surface and a bottom surface deflectably fixed to the top surface by a fixing unit. The first probe and the plurality of second probes protrude from the bottom surface for contacting the first electrode area and the second electrode area respectively. Wherein the first probe is within a periphery surrounded by the plurality of second probes in a vertical direction of the bottom surface.

Abstract: A system includes a factory interface, an etching tool, and at least one measuring device. The factory interface is configured to carry a wafer. The etching tool is coupled to the factory interface and configured to process the wafer transferred from the factory interface. The at least one measuring device is equipped in the factory interface, the etching tool, or the combination thereof. The at least one measuring device is configured to perform real-time measurements of reflectance from the wafer that is carried in the factory interface or the etching tool.

Abstract: Provided is a plant extract-containing composition for reducing skin damage caused by ultraviolet radiation. The composition includes a combination of extracts of spinach, black tea, green tea, Pu-erh tea, Four Seasons Spring tea, red wine, blueberry, grape seeds, citrus, or green coffee beans.

Abstract: A semiconductor device and method of manufacturing the same that utilizes dielectric pedestals on a sensing electrode. The semiconductor device includes a one or more membranes and an integrated circuit substrate. The integrated circuit substrate includes one or more conductive components disposed within a first dielectric layer on the substrate, with the conductive components interconnected with respective integrated circuit components. The substrate further includes one or more sensing electrodes electrically coupled to the conductive components, and one or more dielectric pedestals positioned within a landing area of the sensing electrode. In addition, the semiconductor device includes at least one cavity that is formed by the membrane positioned over the sensing electrode.

Abstract: A rapid heat dissipation device is provided to use for a heat source, and includes a heat conducting plate, a heat dissipating fin group, one or a plurality of heat pipes and a siphon heat-dissipating device. The heat conducting plate is thermally attached to the heat source. The heat dissipating fin group is arranged on one side of the heat conducting plate. One end of the heat pipe is fixed to the heat conducting plate, and another end is fixed to the heat dissipating fin group. The siphon heat-dissipating device is stacked above the heat pipe, and one end is fixed to the heat-conducting plate and another end is fixed to the heat-dissipating fin group. Through the siphon heat-dissipating device overlapping up and down with the heat pipe and having the same direction to achieve uniformly heat dissipating and cooling.

Abstract: A semiconductor device includes a first substrate having opposite first and second sides, a first conductive layer on the first side of the first substrate, and a second substrate having opposite first and second sides. The second side of the second substrate is bonded to the first side of the first substrate. The second substrate includes a semiconductor material, and at least one circuit element electrically coupled to the first conductive layer. The at least one circuit element includes at least one of a Schottky diode configured by the semiconductor material and a first contact structure, a capacitor having a first electrode of the semiconductor material, or a resistor of the semiconductor material.

Abstract: Methods for programming memory cells of a resistive memory device include applying a voltage pulse sequence to a memory cell to set a logic state of the memory cell. An initial set sequence of voltage pulses may be applied to the memory cell, followed by a reform voltage pulse having an amplitude greater than the amplitudes of the initial set sequence, and within ±5% of the amplitude of a voltage pulse used in an initial forming process. Additional voltage pulses having amplitudes that are less than the amplitude of the reform voltage pulse may be subsequently applied. By applying a reform voltage pulse in the middle of, or at the end of, a memory set sequence including multiple voltage pulses, a resistive memory device may have a larger memory window and improved data retention relative to resistive memory devices programmed using conventional programming methods.

Abstract: A package structure includes a first redistribution layer, a semiconductor die, and through vias. The first redistribution layer includes dielectric layers, first conductive patterns, and second conductive patterns. The dielectric layers are located in a core region and a peripheral region of the first redistribution layer. The first conductive patterns are embedded in the dielectric layers in the core region, wherein the first conductive patterns are arranged in the core region with a pattern density that gradually increases or decreases from a center of the core region to a boundary of the core region. The second conductive patterns are embedded in the dielectric layers in the peripheral region. The semiconductor die is disposed on the core region over the first conductive patterns. The through vias are disposed on the peripheral region and electrically connected to the second conductive patterns.

Abstract: A method of controlling chemical concentration in electrolyte includes measuring the chemical concentration in the electrolyte in a tank, wherein an end of an exhaust pipe is connected to a top of the tank; determining, by a valve moved along a top surface of the tank, a vapor flux through the exhaust pipe based on the measured chemical concentration; rotating, by using a motor connected to a ball screw connected to the valve, the ball screw to move a gate of the valve based on the determined vapor flux; electroplating, using the electrolyte provided by the tank, wafers respectively in a plurality of electroplating cells that are connected to the tank; and recycling the electrolyte to the tank.

Abstract: A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region.

Abstract: A rapid heat dissipation device is provided to use for a heat source, and includes a heat conducting plate, a heat dissipating fin group, one or a plurality of heat pipes and a siphon heat-dissipating device. The heat conducting plate is thermally attached to the heat source. The heat dissipating fin group is arranged on one side of the heat conducting plate. One end of the heat pipe is fixed to the heat conducting plate, and another end is fixed to the heat dissipating fin group. The siphon heat-dissipating device is stacked above the heat pipe, and one end is fixed to the heat-conducting plate and another end is fixed to the heat-dissipating fin group. Through the siphon heat-dissipating device overlapping up and down with the heat pipe and having the same direction to achieve uniformly heat dissipating and cooling.

Abstract: A pliers includes a first body with an engaging groove and a second body with an elongated slot pivotally connected with each other. The elongated slot includes a left and right positioning grooves and a protruding portion disposed therebetween. A tap button is pivotally connected to the second body. A supporting member is disposed between the second body and the tap button. When the first body comes close to the second body, the tap button can be tapped to a first position and engaged in the engaging groove. Thus, the first body is blocked and cannot pivot relative to the second body. The tap button can be tapped to a second position and detached from the engaging groove. Thus, the first body is pivotable relative to the second body. A positioning block is extending from the tap button and can be engaged in any of the positioning grooves for positioning the tap button.

Abstract: The present disclosure relates to an integrated chip including a first ferroelectric layer over a substrate. A first electrode layer is over the substrate and on a first side of the first ferroelectric layer. A second electrode layer is over the substrate and on a second side of the first ferroelectric layer, opposite the first side. A first barrier layer is between the first ferroelectric layer and the first electrode layer. A bandgap energy of the first barrier layer is greater than a bandgap energy of the first ferroelectric layer.

Abstract: An optical module includes a housing, a plurality of active optical components and a path changer component. The housing has an airtight chamber. The active optical components are provided in the airtight chamber. The path changer component is provided in the airtight chamber, and the path changer component is configured to change an optical path of at least one of the active optical components.

Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.