Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including an interconnect structure overlying a semiconductor substrate. An upper dielectric structure overlies the interconnect structure. A microelectromechanical system (MEMS) substrate overlies the upper dielectric structure. A cavity is defined between the MEMS substrate and the upper dielectric structure. The MEMS substrate comprises a movable membrane over the cavity. A cavity electrode is disposed in the upper dielectric structure and underlies the cavity. A plurality of stopper structures is disposed in the cavity between the movable membrane and the cavity electrode. A dielectric protection layer is disposed along a top surface of the cavity electrode. The dielectric protection layer has a greater dielectric constant than the upper dielectric structure.

Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, where the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity.

Abstract: A semiconductor process system includes a semiconductor process chamber having an interior volume. A pump extracts gases from the semiconductor process chamber via an outlet channel communicably coupled to the semiconductor process chamber. The system includes a plurality of fluid nozzles configured to prevent the backflow of particles from the outlet channel to interior volume by generating a fluid barrier within the outlet channel responsive to the pump ceasing to function.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.

Abstract: A device model parameter generation system, comprises a user module, for obtaining parameter set configurations and measurement data of devices; a parameter extraction module, for performing parameter extractions on the parameter set configurations and the measurement data, to generate a parameter set; a simulation module, for performing simulations according to the parameter set configurations and the measurement data, to generate a simulation results; an analysis module, for determining whether the devices conform to a trend according to the parameter set, to generate a first determination result, and for determining whether the devices conform to a smoothness according to the first determination result and the parameter set, to generate a second determination result; and a device model parameter generation module, for generating a device model parameters according to the second determination result and the parameter set.

Abstract: A method includes: transferring a wafer from a factory interface through a load lock chamber to a buffer chamber; transferring the wafer from the buffer chamber to a process chamber; etching the wafer in the process chamber, to remove a material of the wafer; and after the wafer is etched, performing reflectance measurements to the wafer in the factory interface, the load lock chamber, the buffer chamber, or combination thereof, to identify if the material of the wafer is removed entirely according to a reflectance of the wafer.

Abstract: An oral pharmaceutical formulation containing an effective amount of NRC-AN-019 including its pharmaceutically acceptable salts and polymorphs thereof, by dispersing in a polymer system in a final state of subdivision to enhance oral bioavailability. It also compositions for the treatment of Chronic Myeloid Leukemia and other tumors such as head and neck cancer, prostate cancer and the like.

Abstract: An electronic whiteboard system includes a data processing equipment receiving a plurality of first editing information provided by at least a portion of a plurality of client-end equipment, sorting and grouping the plurality of first editing information to select and sort from the plurality of first editing information as a plurality of pre-processing information, calculating a plurality of priority scores of the plurality of pre-processing information, sorting the plurality of pre-processing information according to the plurality of priority scores, verifying whether the plurality of pre-processing information sorted according to the priority scores are permitted to select at least one of the plurality of pre-processing information verified as permitted to generate second editing information, and executing the second editing information, so that the plurality of client-end equipment display editing results of a cloud electronic whiteboard corresponding to the second editing information.

Abstract: A composition comprising a grape seed extract and a black tea extract. The composition can increase testosterone secretion more effectively than a single component, and can be used for preparing pharmaceutical compositions, foods, health foods, dietary supplements or drinks used for promoting testosterone secretion.

Abstract: A nitride-based semiconductor device includes a first and a second nitride-based semiconductor layers, a source electrode, a gate electrode, and a drain structure. The drain structure includes a first doped nitride-based semiconductor layer, an ohmic contact electrode, and a conductive layer. The first doped nitride-based semiconductor layer is in contact with the second nitride-based semiconductor layer to form a first contact interface. The ohmic contact electrode is in contact with the second nitride-based semiconductor layer to form a second contact interface. The conductive layer includes metal and in contact with the second nitride-based semiconductor layer to form a metal-semiconductor junction therebetween. The conductive layer is connected to the first doped nitride-based semiconductor layer and the ohmic contact electrode, and the ohmic contact interface is farther away from the gate electrode than the first contact interface and the second contact interface.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The top electrode has interior surfaces defining a recess within an upper surface of the top electrode. A masking layer contacts a bottom of the recess and extends to over the upper surface of the top electrode. An interconnect extends through the masking layer and to the top electrode. The interconnect is directly over the upper surface of the top electrode.

Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.

Abstract: A MEMS package is provided. The MEMS package includes a metallization layer, a planarization structure, a MEMS device structure, a cap structure and a pressure adjustment element. The planarization structure has an inner sidewall defining a first cavity exposing the metallization layer. The MEMS device structure is bonded to the planarization structure. The MEMS device structure includes a movable element over the first cavity. The cap structure is bonded to the MEMS device structure and has an inner sidewall defining a second cavity facing the movable element. The pressure adjustment element is disposed in the second cavity.

Abstract: A semiconductor device includes a substrate having a first conductivity type, a well region having a second conductivity type and disposed on the substrate, a first trench and a second trench disposed in the well region. In addition, a first field plate and a first dielectric layer surrounding the first field plate are disposed in the first trench. A second field plate and a second dielectric layer surrounding the second field plate are disposed in the second trench. A first gate is disposed above the first field plate. A source electrode is disposed on a first side of the first trench, and a drain electrode is disposed on a second side of the second trench. The source electrode, the first trench, the second trench and the drain electrode are sequentially arranged along a first direction.

Abstract: The present disclosure relates to a ferroelectric memory device that includes a bottom electrode, a ferroelectric structure overlying the bottom electrode, and a top electrode overlying the ferroelectric structure where the bottom electrode includes molybdenum.

Abstract: A semiconductor device includes a substrate and a well region both having a first conductivity type, a trench in the substrate and directly above the well region, a first trench gate and a second trench gate disposed in the trench and laterally separated from each other, a dielectric isolation portion disposed in the trench and between the first and second trench gates, and a dielectric liner in the trench and under bottom surfaces of the first and second trench gates. A middle region of a bottom surface of the dielectric isolation portion protrudes downward and is lower than two side regions of the bottom surface of the dielectric isolation portion. Below a horizontal line of the bottom surfaces of the first and second trench gates, the thickness of the dielectric isolation portion is greater than the thickness of the dielectric liner.

Abstract: A semiconductor device includes an epitaxial layer on a substrate, a first body region and a first trench gate structure in the epitaxial layer, a first planar gate and a first source electrode on the epitaxial layer, a first source region in the first body region, and a drain electrode under the substrate. The first trench gate structure is extended along a first direction and adjacent to the first body region. The first planar gate is extended along a second direction and at least partially located directly above the first body region. There is a non-zero included angle between the second direction and the first direction. The first source electrode is extended downward into the first body region. The first source region is at least partially adjacent to the first source electrode.

Abstract: A semiconductor process system includes a semiconductor process chamber having an interior volume. A pump extracts gases from the semiconductor process chamber via an outlet channel communicably coupled to the semiconductor process chamber. The system includes a plurality of fluid nozzles configured to prevent the backflow of particles from the outlet channel to interior volume by generating a fluid barrier within the outlet channel responsive to the pump ceasing to function.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.

Abstract: During operation, a controller node, in multiple nodes in a cluster, may provide to the multiple nodes a set of operations associated with an update of controller software for a controller, where at least the controller node implements the controller. Moreover, at least a first node in the multiple nodes may perform the set of operations associated with the update of the controller software. Furthermore, at least a second node in the multiple nodes may monitor the performing of the set of operations by at least the first node. When the performing of the set of operations is completed by at least the first node, the first node may terminate the performing of the set of operations by the multiple nodes. Alternatively, when a failure occurs during the update of the controller software, at least the first node or the second node may automatically recover the multiple nodes.