Patents by Inventor Fu Lin

Fu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10409485
    Abstract: A user input device for use with a controlled device. The user input device includes a substrate; a plurality of sensing electrodes disposed separately on or in the substrate for sensing an object; and a controller electrically coupled to the sensing electrodes and stored therein at least one virtual key allocation table, wherein the controller executes a converting operation to generate a sensed object information according to a capacitance data realized from the sensing electrodes, and generates an input command associated with a specified key in the virtual key allocation table, which corresponds to the sensed object information, for controlling the controlled device. The same sensed object information can be designed to correspond to keys of different definition under different virtual key allocation tables, and/or derive different input commands in different operational.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: September 10, 2019
    Assignee: TOUCHPLUS INFORMATION CORP.
    Inventors: Shih-Hsien Hu, Yi-Feng Wei, Yao-Chih Chuang, Chao-Fu Lin
  • Publication number: 20190273321
    Abstract: An electronic package and a method for fabricating the same are provided. A resist layer and a support are formed on a first substrate having a first antenna installation area. A second substrate having a second antenna installation area is laminated on the resist layer and the support. The resist layer is then removed. The support keeps the first substrate apart from the second substrate at a distance to ensure that the antenna transmission between the first antenna installation area and the second antenna installation area can function normally.
    Type: Application
    Filed: May 30, 2018
    Publication date: September 5, 2019
    Inventors: Han-Hung Chen, Chun-Yi Huang, Chang-Fu Lin, Rung-Jeng Lin, Kuo-Hua Yu
  • Publication number: 20190265859
    Abstract: The present disclosure provides a touch controller, which includes, a monitoring circuit, configured to configured to detect a sensing signal generated via a touch sensor when a display panel is driven, and obtain at least one synchronizing signal according to the sensing signal; and a touch detecting circuit, configured to output a touch driving signal to the touch sensor according to the synchronizing signal. The touch controller provided by the present disclosure reduces the signal interference between the touch controller and the display driving circuit by using a touch sensor to obtain the synchronizing signal from the display panel.
    Type: Application
    Filed: May 10, 2019
    Publication date: August 29, 2019
    Inventors: YUNG-FU LIN, CHENG-CHUNG HSU
  • Publication number: 20190267492
    Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.
    Type: Application
    Filed: May 15, 2019
    Publication date: August 29, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Yen-Chen Chen, Xiao Wu, Hai Tao Liu, Ming Hua Du, Shouguo Zhang, Yao-Hung Liu, Chin-Fu Lin, Chun-Yuan Wu
  • Publication number: 20190252344
    Abstract: The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.
    Type: Application
    Filed: May 15, 2018
    Publication date: August 15, 2019
    Inventors: Yu-Min Lo, Chee-Key Chung, Chang-Fu Lin, Kuo-Hua Yu, Hsiang-Hua Huang
  • Patent number: 10381228
    Abstract: An epitaxial process applying light illumination includes the following steps. A substrate is provided. A dry etching process and a wet etching process are performed to form a recess in the substrate, wherein an infrared light illuminates while the wet etching process is performed. An epitaxial structure is formed in the recess.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: August 13, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ying Lin, Ted Ming-Lang Guo, Chin-Cheng Chien, Chih-Chien Liu, Hsin-Kuo Hsu, Chin-Fu Lin, Chun-Yuan Wu
  • Patent number: 10382717
    Abstract: A video file playback system capable of previewing an image, a method thereof, and a computer program product can sequentially compare change amounts between chronological two of frame images, select the frame images, of which the change amounts exceed a preset value, in at least one time interval, and select a frame image, which has a maximum change amount, in the frame images in each time interval as a preview image. By displaying a preview image corresponding to each time interval, a user can quickly browse key images of each time interval.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: August 13, 2019
    Assignee: VIVOTEK INC.
    Inventors: Chien-Wen Liu, Yen-Fu Lin, Shih-Wu Fanchiang
  • Publication number: 20190238979
    Abstract: A virtual bass generating circuit used in a speaker is used to filter out a high frequency part of an audio signal to generate a low passed audio signal, generates an even and odd audio signals respectively having even and odd harmonics of the low passed audio signal according to the low passed audio signal, subtracts an amplified low passed audio signal from an addition of an amplified even audio signal and an amplified odd audio signal to generate a first calculated audio signal, filters out a low frequency part and a high frequency part of the first calculated audio signal to generate a band passed audio signal, and adds the band passed audio signal and the audio signal to generate a second calculated audio signal with enhanced even and odd harmonics of the audio signal.
    Type: Application
    Filed: January 31, 2018
    Publication date: August 1, 2019
    Inventors: HSIN-YUAN CHIU, TSUNG-FU LIN
  • Publication number: 20190237374
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes: forming a circuit structure on an encapsulant; embedding a first electronic component and a plurality of conductive posts in the encapsulant; and disposing a second electronic component on the circuit structure. Since the first and second electronic components are arranged on opposite sides of the circuit structure, the electronic package can provide multi-function and high efficiency.
    Type: Application
    Filed: May 4, 2018
    Publication date: August 1, 2019
    Inventors: Chen-Yu Huang, Chee-Key Chung, Chang-Fu Lin, Kong-Toon Ng, Rui-Feng Tai, Bo-Hao Ma
  • Publication number: 20190229053
    Abstract: A manufacturing method of a metal-insulator-metal (MIM) capacitor structure includes the following steps. A bottom plate is formed. A first conductive layer is patterned to be the bottom plate, and the first conductive layer includes a metal element. An interface layer is formed on the first conductive layer by performing a nitrous oxide (N2O) treatment on a top surface of the first conductive layer. The interface layer includes oxygen and the metal element of the first conductive layer. A dielectric layer is formed on the interface layer. A top plate is formed on the dielectric layer. The metal-insulator-metal capacitor structure includes the bottom plate, the interface layer disposed on the bottom plate, the dielectric layer disposed on the interface layer, and the top plate disposed on the dielectric layer.
    Type: Application
    Filed: January 22, 2018
    Publication date: July 25, 2019
    Inventors: Ya-Jyuan Hung, Ai-Sen Liu, Bin-Siang Tsai, Chin-Fu Lin, Chun-Yuan Wu
  • Patent number: 10361150
    Abstract: The disclosure provides a substrate construction applicable to a 3D package, including a silicon substrate for carrying a chip on an upper side thereof, and a circuit structure formed underneath the silicon substrate for being connected to solder balls via conductive pads of the circuit structure, thereby obtaining the same specification of the conductive pads as ball-planting pads of conventional package substrates and avoiding the manufacturing and use of conventional package substrates.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: July 23, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chee-Key Chung, Yu-Min Lo, Han-Hung Chen, Chang-Fu Lin, Fu-Tang Huang
  • Publication number: 20190221528
    Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.
    Type: Application
    Filed: March 22, 2019
    Publication date: July 18, 2019
    Inventors: Chun-Hung Chen, Chu-Fu Lin, Ming-Tse Lin
  • Patent number: 10354891
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming a filling material, such as an underfill, between a carrier and a plurality of electronic components and filling the filling material in a space between the electronic components to form a spacing portion. The spacing portion has a first segment and a second segment separated from each other to serve as a stress buffer zone. Therefore, when an encapsulation layer encapsulating the electronic components is subsequently ground, the present disclosure can effectively prevent the electronic components from being cracked due to stresses induced by the external grinding force.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: July 16, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Po-Hao Wang, Chih-Jen Yang, Yu-Chih Cheng, Chee-Key Chung, Chang-Fu Lin
  • Patent number: 10348030
    Abstract: A socket connector includes an insulating housing, at least one docking element, a plurality of docking terminals, a fastening board and an outer cover assembly. A middle of the insulating housing has at least one holding groove. The at least one docking element is assembled in the at least one holding groove. The at least one docking element defines a plurality of docking grooves. The plurality of the docking terminals are fastened in the plurality of the docking grooves, separately. The fastening board has a first opening. The insulating housing is fastened to a rear surface of the fastening board. The outer cover assembly is assembled in the first opening. The outer cover assembly includes a frame and a waterproof element. The waterproof element has a sleeving ring, a covering portion, and a connecting element connected between the sleeving ring and the covering portion.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: July 9, 2019
    Assignee: CHENG UEI PRECISION INDUSTRY CO., LTD.
    Inventors: Chih-Chiang Lin, Chun-Fu Lin, Te-Hung Yin
  • Patent number: 10340391
    Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: July 2, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Yen-Chen Chen, Xiao Wu, Hai Tao Liu, Ming Hua Du, Shouguo Zhang, Yao-Hung Liu, Chin-Fu Lin, Chun-Yuan Wu
  • Patent number: 10340231
    Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: July 2, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hung Chen, Chu-Fu Lin, Ming-Tse Lin
  • Patent number: 10323332
    Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: June 18, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ling Lin, Yen-Liang Lu, Chi-Mao Hsu, Chin-Fu Lin, Chun-Hung Chen, Tsun-Min Cheng, Chi-Ray Tsai
  • Publication number: 20190181021
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming a filling material, such as an underfill, between a carrier and a plurality of electronic components and filling the filling material in a space between the electronic components to form a spacing portion. The spacing portion has a first segment and a second segment separated from each other to serve as a stress buffer zone. Therefore, when an encapsulation layer encapsulating the electronic components is subsequently ground, the present disclosure can effectively prevent the electronic components from being cracked due to stresses induced by the external grinding force.
    Type: Application
    Filed: April 4, 2018
    Publication date: June 13, 2019
    Inventors: Po-Hao Wang, Chih-Jen Yang, Yu-Chih Cheng, Chee-Key Chung, Chang-Fu Lin
  • Patent number: 10311868
    Abstract: A device performs a method for using image data to aid voice recognition. The method includes the device capturing (302) image data of a vicinity of the device and adjusting (304), based on the image data, a set of parameters for voice recognition performed by the device (102). The set of parameters for the device performing voice recognition include, but are not limited to: a trigger threshold of a trigger for voice recognition; a set of beamforming parameters; a database for voice recognition; and/or an algorithm for voice recognition. The algorithm may include using noise suppression or using acoustic beamforming.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: June 4, 2019
    Assignee: Google Technology Holdings LLC
    Inventors: Robert A. Zurek, Adrian M. Schuster, Fu-Lin Shau, Jincheng Wu
  • Publication number: 20190164861
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes disposing on a carrier an electronic component having a plurality of conductors, encapsulating the electronic component with an encapsulant, and disposing an electronic device on the encapsulant. The electronic device and the carrier are electrically connected through the conductors, thereby reducing the overall thickness of the electronic package.
    Type: Application
    Filed: October 25, 2018
    Publication date: May 30, 2019
    Inventors: Wen-Shan Tsai, Chee-Key Chung, Chang-Fu Lin