Abstract: The present invention provides an electrolyte material formulation including: (a) a monomer of formula (I) (b) a monomer of formula (II) ?and (c) a polymerizable compound, wherein A, X, B1, B2, R1 to R3, q and w are defined as those recited in the specification, and the monomer (b) is in an amount of about 1 part by weight to about 800 parts by weight and the polymerizable compound (c) is in an amount of about 1 part by weight to about 10000 parts by weight based on 100 parts by weight of the monomer (a). The present invention further provides an electrolytic material composition obtained by the polymerization of the aforementioned electrolytic material formulation. The electrolytic material composition can be applied to a solid electrolyte capacitor.

Abstract: An optical sensing module is configured to detect a characteristic of a sample. The optical sensing module includes a light source, a light guide plate, a first cladding layer, a light converging layer, a filter layer, and a plurality of sensors. The light source is configured to provide an exciting beam. Positions of the sensors correspond to positions of the holes. After the exciting beam enters the light guide plate, at least one portion of the exciting beam is transmitted to the sample through a portion of the surface of the light guide plate exposed by the holes, the sample is excited by the exciting beam to emit a signal beam, and the signal beam passes through the light converging layer and the filter layer in an order and travels to the sensors. Another optical sensing module is also provided.

Abstract: A lightweight solar module building materials set includes a solar module, a perforated plate defining multiple perforations, and a support assembly which is essentially composed of a supportive plate and a honeycomb structure and can support the solar module and the perforated plate. The perforated plate, the honeycomb structure, and the supportive plate define multiple sound absorption compartments. Sound waves can enter the sound absorption compartments via the perforations of the perforated plate. The solar module includes a solar cell body, which is protected by a flexible transparent protective layer and supported by the support assembly, to conduct photoelectric conversion. The solar module building materials set can be mounted on an affixing means to construct a sound insulation wall, which can generate solar power and absorb sound waves. As such, the ratio of green energy supply and the comfort of life can be increased.

Abstract: A multi-stage Radio Frequency (RF) power amplifier is presented herein. According to one embodiment, the amplifier comprises: a first amplification stage configured to amplify an input signal to provide a first output signal having a phase distortion; a second amplification stage having an input and configured to amplify the first output signal that is received at the input to provide a second output signal, wherein the second output signal has a carrier frequency (FC) modulated by a signal content (S) having a signal content bandwidth (FS); and a resonant circuit comprising an inductor and a capacitor and having a resonant frequency (FR), the resonant circuit coupled to the input of the second amplification stage and compensating for the phase distortion caused by the first amplification stage at frequencies within the signal content bandwidth FS, wherein the resonant frequency FR is less than the signal content bandwidth FS.

Abstract: The present invention provides a non-planar FET and a method of manufacturing the same. The non-planar FET includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.

Abstract: An electronic package is provided, which includes: a first substrate; a first electronic component disposed on the first substrate; a second substrate stacked on the first substrate through a plurality of first conductive elements and a plurality of second conductive elements and bonded to the first electronic component through a bonding layer; and a first encapsulant formed between the first substrate and the second substrate. The first conductive elements are different in structure from the second conductive elements so as to prevent a mold flow of the first encapsulant from generating an upward pushing force during a molding process and hence avoid cracking of the second substrate. The present disclosure further provides a method for fabricating the electronic package.

Abstract: A liquid crystal display panel includes a first substrate, a second substrate, a third substrate, a pixel electrode layer, a first common electrode layer, a first control electrode layer, a first liquid crystal layer, a second common electrode layer, a second control electrode layer and a second liquid crystal layer. The second substrate is opposite to the first substrate. The third substrate is opposite to the second substrate. The pixel electrode layer and the first common electrode layer are disposed on the first substrate. The first control electrode layer is disposed on the second substrate. The first liquid crystal layer is disposed between the first substrate and the second substrate. The second common electrode layer is disposed on the second substrate. The second control electrode layer is disposed on the third substrate. The second liquid crystal layer is disposed between the second substrate and the third substrate.

Abstract: A package substrate is provided, which includes a plurality of dielectric layers and a plurality of circuit layers alternately stacked with the dielectric layers. At least two of the circuit layers have a difference in thickness so as to prevent warpage of the substrate.

Abstract: A joint orthosis includes upper and lower members, and a joint mechanism. The joint mechanism includes a shielding cover and at least one of modular front and rear inserts. Each of the modular front and rear inserts is disposed to limit movement of a joint of a human body in a flexion/extension direction. The shielding cover is removably attached to a mounting frame of the joint mechanism and is configured to conceal and prevent access to the at least one or the modular front and rear inserts.

Abstract: A sensing module including a sample loading layer, a sensing layer and an optical resonance layer locating between the sample loading layer and the sensing layer is provided. The sample loading layer includes at least a sample loading depression, and the sample loading depression exposes part of the optical resonance layer, and the sample loading depression is adapted to load sample. A surface of the optical resonance layer has optical resonance structures, and the optical resonance structures are located beside bottom of the sample loading depression or below the bottom of the sample loading depression. The sensing layer is configured to receive light and turn it into electrical signals. A sensing method is also provided.

Abstract: Some embodiments of the present disclosure provide an optical sensor. The optical sensor includes a semiconductive substrate; a light sensing region on the semiconductive substrate; a waveguide region configured to guide light from a wave insert portion through a waveguide portion and to a sample holding portion; and an interconnect region below the waveguide region, and the interconnect region being disposed above the light sensing region. The waveguide portion includes a first dielectric layer comprising a first refractive index and at least one second dielectric layer comprising a second refractive index, wherein the second refractive index is smaller than the first refractive index.

Abstract: Methods of testing, manufacturing, and packaging semiconductor devices are disclosed. In some embodiments, a method of testing a semiconductor device includes providing an integrated circuit die having contacts disposed thereon, forming an insulating material over the integrated circuit die and the contacts, and forming an opening in the insulating material over the contacts. A eutectic material is formed in the openings over the contacts, and the integrated circuit die is electrically tested by contacting the eutectic material disposed over the contacts. The eutectic material is removed.

Abstract: A trench power semiconductor device is provided. A trench gate structure of the trench power semiconductor device located in a cell trench of an epitaxial layer includes a first dielectric layer, a second dielectric layer, a gate electrode, a third dielectric layer, and a shielding layer. The second dielectric layer is interposed between the first and third dielectric layers, and the second dielectric layer is made from different material than the first dielectric layer. After performing a selective etching step on the second dielectric layer, a recess can be formed among the first, second and third dielectric layers. The gate electrode includes a conductive layer formed in the recess region, and the shielding electrode is surrounded by the third dielectric layer and insulated from the conductive layer.

Abstract: A semiconductor device is disclosed, which includes: a substrate having a plurality of connecting pads; a semiconductor component having a plurality of bonding pads formed on a surface thereof and corresponding to the connecting pads and a UBM layer formed on the bonding pads; a plurality of conductive elements each having a first conductive portion and a second conductive portion sequentially formed on the UBM layer, wherein the second conductive portion is less in width than the first conductive portion; and a plurality of solder balls formed between the second conductive portions and the connecting pads for connecting the semiconductor component and the substrate, thereby preventing solder bridging from occurring between the adjacent conductive elements and reducing stresses between the conductive elements and the UBM layer.

Abstract: Methods of testing, manufacturing, and packaging semiconductor devices are disclosed. In some embodiments, a method of testing a semiconductor device includes providing an integrated circuit die having contacts disposed thereon, forming an insulating material over the integrated circuit die and the contacts, and forming an opening in the insulating material over the contacts. A eutectic material is formed in the openings over the contacts, and the integrated circuit die is electrically tested by contacting the eutectic material disposed over the contacts. The eutectic material is removed.

Abstract: An optical sensing module is configured to detect a characteristic of a sample. The optical sensing module includes a light source, a light guide plate, a first cladding layer, a light converging layer, a filter layer, and a plurality of sensors. The light source is configured to provide an exciting beam. Positions of the sensors correspond to positions of the holes. After the exciting beam enters the light guide plate, at least one portion of the exciting beam is transmitted to the sample through a portion of the surface of the light guide plate exposed by the holes, the sample is excited by the exciting beam to emit a signal beam, and the signal beam passes through the light converging layer and the filter layer in an order and travels to the sensors. Another optical sensing module is also provided.

Abstract: Some embodiments of the present disclosure provide an optical sensor. The optical sensor includes a semiconductive substrate. A light sensing region is on the semiconductive substrate. A waveguide region is configured to guide light from a wave insert portion through a waveguide portion and to a sample holding portion. The waveguide portion includes a first dielectric layer including a first refractive index. A second dielectric layer includes a second refractive index. The second refractive index is smaller than the first refractive index. A first interconnect portion is positioned in the waveguide portion, configured to transmit electrical signal from the light sensing region to an external circuit. The sample holding portion is over the light sensing region.

Abstract: A semiconductor device including an integrated circuit, a protection layer, and a conductive via is provided. The integrated circuit includes at least one conductive pad. The protection layer covers the integrated circuit. The protection layer includes a contact opening, and the conductive pad is exposed by the contact opening of the protection layer. The conductive via is embedded in the contact opening of the protection layer, and the conductive via is electrically connected to the conductive pad through the contact opening. A method of fabricating the above-mentioned semiconductor device and an integrated fan-out package including the above-mentioned semiconductor device are also provided.

Abstract: Provided is a substrate structure, including a substrate having at least one chamfer formed on a surface thereof, and a plurality of conductive bodies formed to the substrate. Therefore, a stress generated during the packaging process is alleviated through the chamfer, and the substrate structure is prevented from being cracked. An electronic package employing the substrate structure is also provided.

Abstract: A trenched power semiconductor element, a trenched-gate structure thereof being in an element trench of an epitaxial layer and including at least a shielding electrode, a shielding dielectric layer, a gate electrode, an insulating separation layer, and a gate insulating layer. The shielding electrode is disposed at the bottom of the element trench, the shielding dielectric layer is disposed at a lower portion of the element trench, surrounding the shielding electrode to separate the shielding electrode from the epitaxial layer, wherein the top portion of the shielding dielectric layer includes a hole. The gate electrode is disposed above the shielding electrode, being separated from the hole at a predetermined distance through the insulating separation layer. The insulating separation layer is disposed between the shielding dielectric layer and the gate electrode layer to seal the hole.