Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate defining a memory region and a transistor region, an insulating layer is disposed on the substrate, a 2D material layer disposed on the insulating layer, and disposed within the memory and the transistor region, parts of the 2D material layer within the transistor region is used as the channel region of a transistor structure, the transistor structure is disposed on the channel region. And a resistive random access memory (RRAM) located in the memory region, the RRAM includes a lower electrode layer, a resistance transition layer and an upper electrode layer being sequentially located on the 2D material layer and electrically connected to the channel region.

Abstract: The present disclosure provides a package stack structure and a method for manufacturing the same. The method is characterized by stacking coreless circuit portions on the board of an electronic component to reduce the overall thickness of the package stack structure.

Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.

Abstract: The disclosure provides a substrate construction applicable to a 3D package, including a silicon substrate for carrying a chip on an upper side thereof, and a circuit structure formed underneath the silicon substrate for being connected to solder balls via conductive pads of the circuit structure, thereby obtaining the same specification of the conductive pads as ball-planting pads of conventional package substrates and avoiding the manufacturing and use of conventional package substrates.

Abstract: A display device comprising an active area and a surrounding area is provided. The active area includes a common electrode for receiving a common voltage. The surrounding area is located at a side of the active area, and the surrounding area includes a shielding metal layer and a surrounding circuit. The shielding metal layer is electrically isolated from the common electrode and receives a shielding voltage. The surrounding circuit and a first shielding metal are overlapped in a vertical projection direction, and the common voltage is power-isolated from the shielding voltage.

Abstract: A packaging substrate is provided, which includes: a substrate body having a first region with a plurality of conductive pads and a second region adjacent to the first region, and a material layer formed on the second region to prevent the substrate body from warping. An electronic package having the packaging substrate is also provided.

Abstract: A real-time heart rate detection method for use in a real-time heart rate detection system includes: (A) emitting light to a finger to generate reflected light; (B) receiving the reflected light via a sensing unit, to generate at least one initial fingerprint image; (C) generating plural initial waveform information according to the at least one initial fingerprint image; (D) selecting one among plural different bandpass filters, to filter the initial waveform information; (E) calculating an initial heart rate based upon the filtered initial waveform information; (F) checking and computing a frequency range of the obtained initial heart rate, to determine which one of the plural bandpass filters is the most preferable bandpass filter; (G) outputting a final heart rate; and repeating the step (A) to the step (G). The step (G) and the step (F) are performed at least partially in parallel.

Abstract: An exposure time determination method for image sensing operation includes: providing a first stage exposure condition which includes a first exposure time; sensing an image according to the first stage exposure condition to generate a first histogram which has a first histogram brightness maximum, a first histogram brightness minimum, and a first histogram width; increasing or decreasing the first exposure time to a second exposure time as a second stage exposure condition, and sensing the image according to the second stage exposure condition to generate a second histogram which has a second histogram brightness maximum, a second histogram brightness minimum, and a second histogram width; comparing the first histogram width with the second histogram width to generate a comparison result, and determining a third exposure time to be a third stage exposure condition according to the comparison result; and sensing the image according to the third stage exposure condition.

Abstract: The present invention provides an image brightness non-uniformity correction method and an image brightness correction device therefor. The image brightness non-uniformity correction method includes the steps of: (A) generating an initial input image having pixels arranged in a matrix, wherein each pixel has a corresponding pixel brightness and the initial input image has non-uniform brightness; (B) performing a pre-processing procedure on the initial input image, to generate a pre-processed image; (C) performing an image gradient correction procedure on the pre-processed image, to eliminate non-uniformity of the brightness of the initial input image; and (D) outputting an output image having an uniformity-processed brightness.

Abstract: An optical identification method for sensing a physiological feature, includes: projecting light to a physiological portion for generating reflection light from the physiological portion; receiving the reflection light, to generate an image; generating slant pattern information according to the image; transforming the slant pattern information into a pattern identification matrix; and determining the physiological feature according to the pattern identification matrix.

Abstract: An optical identification method, includes: projecting light on a finger to generate reflected light from the finger; receiving the reflected light by a pixel sensing array to obtain a plurality of finger images; and determining whether the finger images present a liveness characteristic, according to a required exposure time or average brightness of the finger images obtained by the pixel sensing array. When the finger images present the liveness characteristic, the optical identification method further includes: determining identification information according to the finger images; or when the finger images do not present the liveness characteristic, the optical identification method further includes: not determining identification information according to the finger images, and optionally, stopping the pixel sensing array from obtaining a subsequent finger image.

Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

Abstract: An operation member for an electronic device is provided. The electronic device includes a casing having portions defining an opening and a circuit module having a circuit board. The circuit board includes a controller. The operation member includes a body including an operating end and a coupling end, and a skirt member. The body is configured to partially protrude through the opening of the casing for operating. The skirt member is arranged at the coupling end. The skirt member includes a base plate outwardly extending from the coupling end, a wall upwardly extending from peripheral portions of the base plate, and a groove defined between the wall and the body. The operation member is configured to associate with the electronic device, and the operation member with the body and the skirt is completely separated from the casing.

Abstract: A trench power semiconductor device is provided. A trench gate structure of the trench power semiconductor device located in a cell trench of an epitaxial layer includes a first dielectric layer, a second dielectric layer, a gate electrode, a third dielectric layer, and a shielding layer. The second dielectric layer is interposed between the first and third dielectric layers, and the second dielectric layer is made from different material than the first dielectric layer. After performing a selective etching step on the second dielectric layer, a recess can be formed among the first, second and third dielectric layers. The gate electrode includes a conductive layer formed in the recess region, and the shielding electrode is surrounded by the third dielectric layer and insulated from the conductive layer.

Abstract: A method of forming a package and a package are provided. The method includes placing a main die and a dummy die side by side on a carrier substrate. The method also includes forming a molding material along sidewalls of the main die and the dummy die. The method also includes forming a redistribution layer comprising a plurality of vias and conductive lines over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die. The method also includes removing the carrier substrate.

Abstract: A semiconductor structure includes a capacitor. The capacitor includes a bottom electrode, a first high-k dielectric layer, a second high-k dielectric layer and a top electrode. The bottom electrode includes a first layer and a second layer disposed on the first layer. The bottom electrode is formed of TiN. The first layer has a crystallization structure. The second layer has an amorphous structure. The first high-k dielectric layer is disposed on the bottom electrode. The first high-k dielectric layer is formed of TiO2. The second high-k dielectric layer is disposed on the first high-k dielectric layer. The second high-k dielectric layer is formed of a material different from TiO2. The top electrode is disposed on the second high-k dielectric layer.

Abstract: The present invention provides a capacitor structure, including a bottom plate and a top plate, wherein the top plate has a first sidewall, and wherein an area of the top plate is less than an area of the bottom plate. The capacitor structure further includes a dielectric layer in between the bottom plate and the top plate, the dielectric layer having a second sidewall, wherein the first sidewall is aligned with the second sidewall, and at least one sidewall spacer placed against the first sidewall of the top plate and the second sidewall of the dielectric layer, and overlaying a portion of the bottom plate.

Abstract: A package stack structure is provided, including a first substrate, a second substrate stacked on the first substrate, and an encapsulant formed between the first substrate and the second substrate. A through hole is formed to penetrate the second substrate and allow the encapsulant to be filled therein, thereby increasing the contact area and hence strengthening the bonding between the encapsulant and the second substrate.

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.

Abstract: An integrated circuit and an operation method of a SERDES PHY layer circuit thereof are provided. When the SERDES PHY layer circuit is in a calibration preparation state and a signal of a first calibration input pin is an enable state, or when the SERDES PHY layer circuit is in the calibration preparation state, and signals of first and second calibration input pins are in the enable state, the SERDES PHY layer circuit enters a calibration state (using a reference resistor for current calibration). After the current calibration is completed, the SERDES PHY layer circuit enters a calibration completion state (without using the reference resistor and connecting the first calibration input pin to the first calibration output pin). The SERDES PHY layer circuit sets the signal of the first calibration output pin to a disable state when the SERDES PHY layer circuit is not in the calibration completion state.