Patents by Inventor Fu Lin

Fu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190155178
    Abstract: An apparatus for cleaning an electrostatic reticle holder used in a lithography system includes a chamber for providing a low pressure environment for the electrostatic reticle holder and an ultrasound transducer configured to apply ultrasound waves to the electrostatic reticle holder. The apparatus further includes a controller configured to control the ultrasound transducer and a gas flow controller. The gas flow controller is configured to enable pressurizing or depressurizing the chamber.
    Type: Application
    Filed: February 22, 2018
    Publication date: May 23, 2019
    Inventors: Yu-Fu LIN, Tung-Jung CHANG, Chia-Chen CHEN
  • Publication number: 20190148305
    Abstract: A method of forming a package and a package are provided. The method includes placing a main die and a dummy die side by side on a carrier substrate. The method also includes forming a molding material along sidewalls of the main die and the dummy die. The method also includes forming a redistribution layer comprising a plurality of vias and conductive lines over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die. The method also includes removing the carrier substrate.
    Type: Application
    Filed: December 20, 2018
    Publication date: May 16, 2019
    Inventors: Yan-Fu Lin, Chen-Hua Yu, Meng-Tsan Lee, Wei-Cheng Wu, Hsien-Wei Chen
  • Publication number: 20190143457
    Abstract: A laser preheating control method is applied to a laser preheating control device. When a cutter processes a workpiece along a process path, a laser source of the device is provided to output a laser beam to the workpiece for selectively forming a laser spot on the workpiece surface. And according to a movement direction of the cutter, a laser controller of the device is provided to form the laser spot only on a preheating region of the workpiece, where in front of the cutter in the process path, for preheating the workpiece in the preheating region. As a result, the laser spot will not repeatedly heat the workpiece behind the cutter in the process path, and the qualitative change of the workpiece caused by repeating heating is preventable.
    Type: Application
    Filed: December 26, 2017
    Publication date: May 16, 2019
    Inventors: Yu-Ting Lu, Yu-Fu Lin, Jui-Teng Chen, Wen-Long Chang, Chih-Hung Chou
  • Patent number: 10290710
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first gradient layer, two source/drain structures, a second gradient layer, and a gate. The first gradient layer is disposed on the substrate. The two source/drain structures are separately disposed on the first gradient layer. The second gradient layer is disposed on the two source/drain structures and the first gradient layer, and a second portion of the second gradient layer directly contacts a first portion of the first gradient layer. The gate is disposed on the second gradient layer, between the two source/drain structures.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: May 14, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Ming-Chang Lu, Wei Chen, Hui-Lin Wang, Yi-Ting Liao, Chin-Fu Lin
  • Publication number: 20190123424
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes stacking an antenna board on a circuit board, and disposing between the antenna board and the circuit board a supporting body securing the antenna board and the circuit board. As such, during a packaging process, the distance between the antenna board and the circuit board is kept unchanged due to the supporting body, thus ensuring that the antenna board operates properly and improving the product yield.
    Type: Application
    Filed: April 24, 2018
    Publication date: April 25, 2019
    Inventors: Shi-Min Zhou, Han-Hung Chen, Rung-Jeng Lin, Kuo-Hua Yu, Chang-Fu Lin
  • Publication number: 20190107916
    Abstract: A signal processing method for a touch panel includes transmitting a first driving signal to a first touch channel of the touch panel; and transmitting a second driving signal to a second touch channel of the touch panel, wherein the second touch channel is neighboring to the first touch channel. The first driving signal is substantially identical to the second driving signal during a first period, and the first driving signal is substantially inverse to the second driving signal during a second period neighboring to the first period.
    Type: Application
    Filed: October 6, 2017
    Publication date: April 11, 2019
    Inventors: Hung-Cheng Kuo, Yung-Fu Lin, Chun-Hung Chen, Ting-Hsuan Hung
  • Publication number: 20190079418
    Abstract: The present disclosure provides an exhaust system for discharging from semiconductor manufacturing equipment a hazardous gas. The exhaust system includes: a main exhaust pipe having a top surface and a bottom surface; a first branch pipe including an upstream end coupled to a source of a gas mixture containing the hazardous gas and a downstream end connected to the main exhaust pipe through the top surface; a second branch pipe including a downstream end connected to the main exhaust pipe through the bottom surface; and a detector configured to detect presence of the hazardous gas in the second branch pipe.
    Type: Application
    Filed: September 14, 2017
    Publication date: March 14, 2019
    Inventors: Yu-Fu Lin, Shih-Chang Shih, Chia-Chen Chen
  • Publication number: 20190074357
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first gradient layer, two source/drain structures, a second gradient layer, and a gate. The first gradient layer is disposed on the substrate. The two source/drain structures are separately disposed on the first gradient layer. The second gradient layer is disposed on the two source/drain structures and the first gradient layer, and a second portion of the second gradient layer directly contacts a first portion of the first gradient layer. The gate is disposed on the second gradient layer, between the two source/drain structures.
    Type: Application
    Filed: September 5, 2017
    Publication date: March 7, 2019
    Inventors: Kuo-Chih Lai, Ming-Chang Lu, Wei Chen, Hui-Lin Wang, Yi-Ting Liao, Chin-Fu Lin
  • Patent number: 10217754
    Abstract: Provided is a method of fabricating a memory device including performing an ion implantation process by using a mask layer as an implanting mask, so as to form a first embedded doped region and a second embedded doped region in a substrate. The first embedded doped region extends along the first direction, passes through the control gate, and is electrically connected to the first doped region, the second doped region and the third doped region at two sides of control gates. The second embedded doped region extends along the second direction, is located in the substrate under the third doped region, and electrically connected to the third doped region. The first embedded doped region is electrically connected to the second embedded doped region.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: February 26, 2019
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Ya-Jung Tsai, Chun-Lien Su, Hsin-Fu Lin, Hung-Chi Chen
  • Patent number: 10216017
    Abstract: A liquid crystal display panel includes a first substrate, a second substrate, a third substrate, a pixel electrode layer, a first common electrode layer, a first control electrode layer, a first liquid crystal layer, a second common electrode layer, a second control electrode layer and a second liquid crystal layer. The second substrate is opposite to the first substrate. The third substrate is opposite to the second substrate. The pixel electrode layer and the first common electrode layer are disposed on the first substrate. The first control electrode layer is disposed on the second substrate. The first liquid crystal layer is disposed between the first substrate and the second substrate. The second common electrode layer is disposed on the second substrate. The second control electrode layer is disposed on the third substrate. The second liquid crystal layer is disposed between the second substrate and the third substrate.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: February 26, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Wan-Heng Chang, Chen-Feng Fan, Rong-Fu Lin, Sung-Yu Su, Hsiao-Wei Cheng
  • Publication number: 20190057917
    Abstract: An electronic package and a method of fabricating the same are provided. The method includes disposing an electronic component on a first side of an interposer, forming a first encapsulant on the first side of the interposer to encapsulate the electronic component, forming a plurality of conductive elements on a second side of the interposer, and forming a second encapsulant on the second side of the interposer to encapsulate the conductive elements. During thermal cycling of the electronic package, shrinkage forces of the first encapsulant and the second encapsulant can offset each other so as to mitigate warping of the interposer.
    Type: Application
    Filed: January 2, 2018
    Publication date: February 21, 2019
    Inventors: Wen-Shan Tsai, Chee-Key Chung, Chang-Fu Lin
  • Patent number: 10192808
    Abstract: A semiconductor structure includes a substrate having a frontside surface and a backside surface. A through-substrate via extends into the substrate from the frontside surface. The through-substrate via comprises a top surface. A metal cap covers the top surface of the through-substrate via. A plurality of cylindrical dielectric plugs is embedded in the metal cap. The cylindrical dielectric plugs are distributed only within a central area of the metal cap. The central area is not greater than a surface area of the top surface of the through-substrate via.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: January 29, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Teng-Chuan Hu, Chun-Hung Chen, Chu-Fu Lin, Chun-Ting Yeh, Chung-Hsing Kuo, Ming-Tse Lin
  • Publication number: 20190013259
    Abstract: A semiconductor structure includes a substrate having a frontside surface and a backside surface. A through-substrate via extends into the substrate from the frontside surface. The through-substrate via comprises a top surface. A metal cap covers the top surface of the through-substrate via. A plurality of cylindrical dielectric plugs is embedded in the metal cap. The cylindrical dielectric plugs are distributed only within a central area of the metal cap. The central area is not greater than a surface area of the top surface of the through-substrate via.
    Type: Application
    Filed: July 6, 2017
    Publication date: January 10, 2019
    Inventors: Teng-Chuan Hu, Chun-Hung Chen, Chu-Fu Lin, Chun-Ting Yeh, Chung-Hsing Kuo, Ming-Tse Lin
  • Publication number: 20190006519
    Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.
    Type: Application
    Filed: June 29, 2017
    Publication date: January 3, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Yen-Chen Chen, Xiao Wu, Hai Tao Liu, Ming Hua Du, Shouguo Zhang, Yao-Hung Liu, Chin-Fu Lin, Chun-Yuan Wu
  • Patent number: 10163802
    Abstract: A method of forming a package and a package are provided. The method includes placing a main die and a dummy die side by side on a carrier substrate. The method also includes forming a molding material along sidewalls of the main die and the dummy die. The method also includes forming a redistribution layer comprising a plurality of vias and conductive lines over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die. The method also includes removing the carrier substrate.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semicondcutor Manufacturing Company, Ltd.
    Inventors: Yan-Fu Lin, Chen-Hua Yu, Meng-Tsan Lee, Wei-Cheng Wu, Hsien-Wei Chen
  • Publication number: 20180364596
    Abstract: A method for creating a vacuum in a load lock chamber is provided. The method includes building an air-tight environment in the load lock chamber. The method further includes reducing the pressure in a gas tank to a predetermined vacuum pressure. The method also includes enabling an exchange of gas between the load lock chamber and the gas tank when the pressure in the gas tank is at the predetermined vacuum pressure so as to reduce the pressure in the load lock chamber to an adjusted vacuum pressure.
    Type: Application
    Filed: June 14, 2017
    Publication date: December 20, 2018
    Inventors: Tung-Jung CHANG, Yu-Fu LIN, Sheng-Kang YU
  • Patent number: 10156794
    Abstract: Positioning devices and positioning methods are provided. The positioning device includes a laser source and an optical assembly. The optical assembly is configured to direct a laser beam projected from the laser source toward a floor and a ceiling of a semiconductor fabrication facility to generate a first laser line on the floor and a second laser line on the ceiling. The first laser line and the second laser line are parallel to and aligned with each other when viewed in a direction perpendicular to the floor and the ceiling. Accordingly, the first laser line and the second laser line can be used to align a semiconductor tool and an overhead hoist transport system in the semiconductor fabrication facility.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Kang Yu, Yu-Fu Lin, Chia-Chen Chen
  • Patent number: 10141193
    Abstract: A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: November 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • Patent number: 10128368
    Abstract: A double gate trench power transistor and manufacturing method thereof are provided. The double gate trench power transistor gate structure includes an epitaxial layer, a trench structure formed in the epitaxial layer, at least two gate structures, and a shielding electrode structure. The trench structure includes a deep trench portion and two shallow trench portions respectively adjacent to two opposite sides of the deep trench portion. Each of the gate structures formed in each of the shallow trench portions includes a gate insulating layer and a gate electrode. The gate insulating layer has a first dielectric layer, a second dielectric layer and a third dielectric layer. The second dielectric layer is interposed between the first and third dielectric layers. Additionally, a portion of the gate insulating layer is in contact with a shielding dielectric layer of the shielding electrode structure.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: November 13, 2018
    Assignee: SINOPOWER SEMICONDUCTOR, INC.
    Inventors: Po-Hsien Li, Jia-Fu Lin, Chia-Cheng Chen, Wei-Chieh Lin
  • Patent number: 10126472
    Abstract: A multi-band spectrum division device is provided, comprising: a first parabolic reflection mirror, planar multi-mirrors, an optical grating and a second parabolic mirror. The first parabolic mirror is configured to reduce the divergent angle of incident optical beam, and to generate a collimated optical beam. The planar multi-mirrors are configured to adjust the incident angles of collimated beam on the grating surface. The grating is configured to disperse the incident signals with multi-wavelengths. The second parabolic mirror is configured to focus the multi-wavelength signals on its focal plane. Besides, each of the planar multi-mirrors has different location and angle in this device.
    Type: Grant
    Filed: September 5, 2016
    Date of Patent: November 13, 2018
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Jyh-Rou Sze, Po-Jui Chen, Chun-Fu Lin