Patents by Inventor Fu Tsai

Fu Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200051147
    Abstract: Systems and methods are disclosed for the functional decomposition of the catalog domain and its sub-domains inside a global scale e-commerce system into respective software application services with dedicated data storage, so in order for the complex raw data of different nature or sub-domain that belongs to large catalogs to be easily accessed and read by online stores, it needs to be deciphered and derived by its domain specific computational process then materialized into appropriate real time content that can be directly obtained via software services and APIs by B2C and B2B websites instead having to utilize lots of computational power for every on line store page request to generate necessary real time content from the same raw catalog data that is administered by catalog managers. In the case of data that does not frequently change (i.e.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Applicant: Digital River, Inc.
    Inventors: Billy Chi Hsun Tsai, Ming-Wei Yang, Ping-Tai Teng Teng, Yung-Fu Tsai
  • Patent number: 10510635
    Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Tu, Hsien-Wei Chen, Tsung-Fu Tsai, Wen-Hsiung Lu, Yian-Liang Kuo
  • Publication number: 20190379260
    Abstract: An angular position sensing device for detecting angular position of a rotor of a motor includes a first resolver that includes an annular rotor, an annular stator, a plurality of excitation coils and four induction coils. The annular stator has a stator annular body, and a plurality of stator magnetic poles. One of the annular rotor and the annular stator surrounds the other one of the annular rotor and the annular stator. The excitation coils are respectively wound on the stator magnetic poles of the annular stator. The induction coils are respectively wound on four of the stator magnetic poles.
    Type: Application
    Filed: June 7, 2018
    Publication date: December 12, 2019
    Inventors: MING-FU TSAI, WEI-TE CHUANG, CHIA-HSIANG LIEN, ZHE-WEI ZHANG
  • Patent number: 10504515
    Abstract: A voice control device includes a microphone module, a voice encoding module, a display and a processing unit. The voice encoding module is electrically connected to the microphone module. The processing unit is electrically connected to the voice encoding module and the display. The microphone module receives a voice signal and transmits the received voice signal to the voice encoding module. One of the voice encoding module and the processing unit analyzes and processes the voice signal to determine a sound source direction of the voice signal and obtains response information according to the voice signal. The processing unit controls the display to rotate to the sound source direction and transmits the response information to the display for displaying the response information.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 10, 2019
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Yu-Yang Chih, Ming-Chun Ho, Ming-Fu Tsai, Cheng-Ping Liu, Fu-Bin Wang, Shih-Lun Lin
  • Patent number: 10461223
    Abstract: A semiconductor device includes a semiconductor stack comprising a surface, and an electrode structure comprises an electrode pad formed on the surface, and the electrode structure further comprises a first extending electrode, a second extending electrode and a third extending electrode connecting to the electrode pad. The first extending electrode is closer to a periphery of the surface than the third extending electrode is, and the second extending electrode is between the first extending electrode and the third extending electrode. From a top view of the semiconductor device, the first extending electrode, the second extending electrode and the third extending electrode respectively include a first curve having a first angle ?1, a second curve having a second angle ?2 and a third curve having a third angle ?3, wherein ?3>?2>?1 .
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: October 29, 2019
    Assignee: Epistar Corporation
    Inventors: Yung-Fu Chang, Hsin-Chan Chung, Hung-Ta Cheng, Wen-Luh Liao, Shih-Chang Lee, Chih-Chiang Lu, Yi-Ming Chen, Yao-Ning Chan, Chun-Fu Tsai
  • Patent number: 10453818
    Abstract: A chip includes a first group of dummy bumps disposed at a top surface of the chip in a first corner of the chip, a second group of dummy bumps disposed at the top surface of the chip in a second corner of the chip, and active bump connectors disposed at the top surface of the chip. The chip also includes an outer seal ring disposed around a periphery of the chip, a first seal ring arrangement disposed around the first group of dummy bumps, and a second seal ring arrangement disposed around the second group of dummy bumps. The first seal ring arrangement and second seal ring arrangement are disposed in dielectric layers underlying the first and second groups of dummy bumps.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: October 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Chia-Wei Tu, Yian-Liang Kuo, Ru-Ying Huang
  • Patent number: 10454879
    Abstract: A method and system for processing Domain Name Services (DNS) request in a gateway. The gateway receives a DNS request from a host from its local area network. The gateway then selects DNS server(s) and transmits a new DNS request to at least one DNS server(s). DNS server(s) may or may not be accessible through a first tunnel. The contents of the new DNS request are the same as the content of the received DNS request. Further, when the gateway receives a DNS response corresponding to the DNS request, it determines a decision whether to transfer data to the host whose IP address is specified in the DNS response through a second tunnel. The decision may be based on a geographical location of an IP address.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: October 22, 2019
    Assignee: PISMO LABS TECHNOLOGY LIMITED
    Inventors: Alex Wing Hong Chan, Ho Ming Chan, Kit Wai Chau, Chi Pan Yip, Min-Fu Tsai
  • Patent number: 10435425
    Abstract: Disclosed herein a sialyl donor and its use for the synthesis of gangliosides. The sialyl donor has the structure of, wherein, R1 and R2 are independently benzoyl, toluenesulfonyl, pivaloyl or acetyl optionally substituted with a halogen; and R3 is acetyl or —(O)CCH2OH. In one preferred embodiment, in the sialyl donor of formula (I), R is acetyl. Also disclosed herein is a method of synthesizing a sialoside. The method comprises steps of: coupling the sialyl donor of formula (I) with a glycosyl acceptor having a primary hydroxyl group in the presence of N-iodosuccinimide (NIS) and trifluoromethanesulfonic acid (TfOH) under suitable conditions; and isolating the sialoside, which has an ?-glycosidic linkage. According to preferred embodiments, the coupling is conducted in a solvent selected from the group consisting of, CH3CN, CH3Cl, and CH2Cl2 at a temperature between ?20° C. to ?60° C.
    Type: Grant
    Filed: July 14, 2018
    Date of Patent: October 8, 2019
    Assignee: Chung Yuan Christian University
    Inventors: Yow-Fu Tsai, Yu-Fa Wu
  • Patent number: 10402207
    Abstract: A system for chassis management includes a plurality of motherboards of a chassis, a plurality of baseboard management controllers (BMCs), and at least one chassis level component. Each of the plurality of BMCs is associated with one of the plurality of motherboards. The plurality of BMCs are interconnected via a first communication bus. The plurality of BMCs and the at least one chassis level component are interconnected via a second communication bus. One BMC of the plurality of BMCs is configured to operate as a virtual chassis management controller (VCMC) for the chassis. The VCMC is configured to exchange data with other BMCs of the plurality of BMCs over the first communication bus and manage the at least one chassis level component over the second communication bus.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: September 3, 2019
    Assignee: QUANTA COMPUTER INC.
    Inventors: Kai-Fan Ku, Chin-Fu Tsai
  • Publication number: 20190251699
    Abstract: An optical projector module to establish distance to target object in a field of view for three dimensional image acquisition purposes includes a printed circuit board, point light sources mounted on the printed circuit board to emit a plurality of light beams, a lens unit apart from the plurality of point light sources, and a distance adjusting unit connected to the lens unit. A memory storage device is also included. The lens unit comprises separated lenses, the adjusting unit can adjust distances between the lenses of the lens unit, and light beams with a number of light spot patterns can accordingly be projected. Previously-captured images in the memory storage device can be referred to in seeking target objects in the field of view and light beams in different spot-concentrations on or around the target object enable calculations for the capture of images in three dimensions of the target object.
    Type: Application
    Filed: January 30, 2019
    Publication date: August 15, 2019
    Inventors: YU-YANG CHIH, MING-FU TSAI, HSUEH-FENG HSU
  • Patent number: 10349016
    Abstract: A color filter array for an image sensing device includes a plurality of pixels, for generating a plurality of pixel data of an image; and a control unit, for controlling the plurality of pixels; wherein each of the plurality of pixels is divided into a plurality of sub-pixels; wherein the pixel data outputted by each of the plurality of pixels is generated based on at least one pixel value of the plurality of sub-pixels and the outputted pixel data is smaller than a saturated threshold; wherein at least one pixel in the plurality of pixels has a mixed color by having different sub-pixel colors in the plurality of sub-pixels.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: July 9, 2019
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Wei Hsu, Shen-Fu Tsai, I-Hsiu Chen
  • Publication number: 20190171198
    Abstract: A semiconductor manufacturing system includes an operating terminal, a first controller, and a plurality of second controllers. The operating terminal controls a main controller. Each of the plurality of second controllers is electrically connected to the first controller. In an initial or default state, the operating terminal controls the first controller as a main controller, and when the first controller fails, the operating terminal controls one of the plurality of the second controllers as a main controller, the others of the plurality of second controllers being controlled by the main controller.
    Type: Application
    Filed: May 28, 2018
    Publication date: June 6, 2019
    Inventors: YI-CHUN CHIU, CHUN-KAI HUANG, CHIH-CHENG LU, CHUN-CHUNG CHEN, CHEN-TSU FU, SHENG-FU TSAI
  • Publication number: 20190171941
    Abstract: An electronic device comprises a data transmitting interface configured to transmit data, a memory configured to store the data, a processor configured to execute an application program, and an accelerator coupled to the processor via a bus. According to an operation request transmitted from the processor, the accelerator reads the data from the memory, performs an operation to the data to generate computed data, and stores the computed data in the memory. The electronic device can improve computational efficiency. An accelerator and an accelerating method applicable to a neural network operation are also provided.
    Type: Application
    Filed: November 29, 2018
    Publication date: June 6, 2019
    Inventors: Nhon-Toai QUACH, Chung-Chieh CHEN, Kong-Qiao WANG, Wen-Fu TSAI, Tzu-Wei YEH, Chung-Hao CHENG, Hui-Min LU
  • Publication number: 20190139802
    Abstract: A front opening unified pod (FOUP) loading and air filling system comprises a FOUP loading device and an air filling device. The FOUP loading device is configured to load and unload a FOUP, and comprises a substrate and a controller. The substrate comprises a frame, a bearing platform installed on the frame, and a cavity under the bearing platform. The bearing platform is configured to support the FOUP. The controller and the air filling device are accommodated in the cavity. The air filling device is connected to the FOUP.
    Type: Application
    Filed: December 7, 2017
    Publication date: May 9, 2019
    Inventors: YI-CHUN CHIU, CHUN-KAI HUANG, CHIH-CHENG LU, CHUN-CHUNG CHEN, CHEN-TSU FU, SHENG-FU TSAI
  • Patent number: 10284190
    Abstract: A voltage detector includes a first node configured to have a first supply voltage, a second node configured to have a second supply voltage, and an output node. The voltage detector is configured to drive the output node to the first supply voltage in response to a difference between the first supply voltage and the second supply voltage exceeding a predetermined threshold voltage value.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Fu Tsai, Jen-Chou Tseng, Kuo-Ji Chen, Tzu-Heng Chang
  • Patent number: 10269762
    Abstract: A rework process includes attaching a first bond head to a first semiconductor package. The contact pads of the first semiconductor package are bonded to contact pads of a second semiconductor package by solder joints. The rework process further includes performing a first local heating process to melt the solder joints, removing the first semiconductor package using the first bond head, and removing at least a portion of solder from the contact pads of the second semiconductor package.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Ting Lin, Justin Huang, Tsung-Fu Tsai, Jing-Cheng Lin, Chen-Hua Yu
  • Patent number: 10269750
    Abstract: Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Tu, Yian-Liang Kuo, Tsung-Fu Tsai, Ru-Ying Huang, Ming-Song Sheu, Hsien-Wei Chen
  • Publication number: 20190109129
    Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the substrate, and a first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and is spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and is spaced apart from the first and second conductive pads. A fourth conductive pad is disposed over the interconnect structure and is spaced apart from the first, second, and third conductive pads. A first ESD protection element is electrically coupled between the first and second pads; and a second ESD protection element is electrically coupled between the third and fourth pads. A first device under test is electrically coupled between the first and third conductive pads; and a second device under test is electrically coupled between the second and fourth pads.
    Type: Application
    Filed: November 28, 2018
    Publication date: April 11, 2019
    Inventors: Jen-Chou Tseng, Ming-Fu Tsai, Tzu-Heng Chang
  • Publication number: 20190081213
    Abstract: A semiconductor device includes a semiconductor stack comprising a surface, and an electrode structure comprises an electrode pad formed on the surface, and the electrode structure further comprises a first extending electrode, a second extending electrode and a third extending electrode connecting to the electrode pad. The first extending electrode is closer to a periphery of the surface than the third extending electrode is, and the second extending electrode is between the first extending electrode and the third extending electrode.
    Type: Application
    Filed: September 12, 2018
    Publication date: March 14, 2019
    Inventors: Yung-Fu CHANG, Hsin-Chan CHUNG, Hung-Ta CHENG, Wen-Luh LIAO, Shih-Chang LEE, Chih-Chiang LU, Yi-Ming CHEN, Yao-Ning CHAN, Chun-Fu TSAI
  • Publication number: 20190074208
    Abstract: A wafer supporting system includes a supporting pedestal. The supporting pedestal includes a main supporting body and a hollow frame surrounding the supporting pedestal. The main supporting body includes a top surface and a bottom surface opposite to the top surface, the top surface defined a plurality of vent grooves and a plurality of holding grooves. The main supporting body includes a plurality of holding channels extending through from the bottom surface to the holding grooves and a plurality of first through holes pass through from the top surface to the bottom surface, each holding groove is surrounded by a plurality of first through holes; an inner side surface of the hollow frame and a side wall of the supporting pedestal form a gap, and a plurality of exhaust cylinders are arranged in the annular gap and each exhaust cylinder is communicated with each vent groove.
    Type: Application
    Filed: June 11, 2018
    Publication date: March 7, 2019
    Inventors: YI-CHUN CHIU, CHUN-KAI HUANG, CHIH-CHENG LU, CHUN-CHUNG CHEN, CHEN-TSU FU, SHENG-FU TSAI