Patents by Inventor Fu Tsai

Fu Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210202436
    Abstract: A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.
    Type: Application
    Filed: June 1, 2020
    Publication date: July 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kung-Chen Yeh, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih
  • Publication number: 20210202455
    Abstract: A package structure includes a circuits substrate, a semiconductor package, a lid structure and a plurality of first spacer structures. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package, wherein the lid structure is attached to the circuit substrate through an adhesive material. The plurality of first spacer structures is surrounding the semiconductor package, wherein the first spacer structures are sandwiched between the lid structure and the circuit substrate, and includes a top portion in contact with the lid structure and a bottom portion in contact with the circuit substrate.
    Type: Application
    Filed: July 9, 2020
    Publication date: July 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Fu Tsai, Chin-Fu Kao, Pu Wang, Szu-Wei Lu
  • Publication number: 20210180952
    Abstract: A microelectromechanical gyroscope system is provided. The system includes a first substrate, a second substrate, and a third substrate. The substrates respectively have a first fixing, a second fixing, and a third fixing surfaces. The system further includes a first sensing, a second sensing and a third sensing module boards respectively fixed to the fixing surfaces. Each sensing module board has several microelectromechanical gyroscopes. A signal processing control board is electrically connected to the first sensing module board, the second sensing module board, and the third sensing module board. Wherein the first substrate, the second substrate, and the third substrate are perpendicular to each other. With the above structure, on each system coordinate axis of the microelectromechanical gyroscope system, at least one gyroscope is aligned with it for data acquisition and measurement. Accordingly, the measurement accuracy of the system is improved.
    Type: Application
    Filed: April 3, 2020
    Publication date: June 17, 2021
    Applicant: National Applied Research Laboratories
    Inventors: Yung-Fu Tsai, Yeong-Wei Wu, Min-Yu Hsieh, Kuo-Liang Wu, Ying-Wen Jan, Chen-Tsung Lin
  • Publication number: 20210167024
    Abstract: A package structure is provided. The package structure includes a through substrate via structure, a first stacked die package structure, an underfill layer, and a package layer. The through substrate via structure is formed over a substrate. The first stacked die package structure is over the through substrate via structure. The first stacked die package structure includes a plurality of memory dies. The underfill layer is over the first stacked die package structure. The underfill layer includes a first protruding portion that extends below a top surface of the through substrate via structure. The package layer is over the underfill layer. The package layer has a second protruding portion that extends below the top surface of the through substrate via structure.
    Type: Application
    Filed: February 9, 2021
    Publication date: June 3, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu TSAI, Kung-Chen YEH, I-Ting HUANG, Shih-Ting LIN, Szu-Wei LU
  • Publication number: 20210143740
    Abstract: A controller for a power converter includes: a first sense terminal and a second sense terminal for sensing an output voltage of the power converter; a bridging circuit configured to electrically couple the first sense terminal to the second sense terminal in a first state and electrically decouple the first sense terminal from the second sense terminal in a second state; and control circuitry configured to set the bridging circuit in the first state during a portion of a voltage ramp of the power converter, and to determine whether an open or short fault condition is present at either the first sense terminal or the second sense terminal based on a voltage across the bridging circuit in the first state.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 13, 2021
    Inventors: Mattia Oddicini, Kelsey Curtis, Tim Ng, Cha-Fu Tsai
  • Patent number: 10985140
    Abstract: A structure and a formation method of a package structure are provided. The method includes disposing a semiconductor die structure over a substrate. The method also includes disposing a protective film over the substrate. The protective film has an opening exposing the semiconductor die structure, and sidewalls of the opening surround the semiconductor die structure. The method further includes dispensing an underfill material into the opening to surround the semiconductor die structure.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: April 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hsuan Tsai, Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu
  • Publication number: 20210112123
    Abstract: A method and system for transmitting and receiving data packets between two network nodes via one or more end-to-end connections. An interface is provided for selecting one or more possible end-to-end connection(s) or established end-to-end connection(s). The method and system may further comprise receiving a policy, wherein one or more selected end-to-end connections are established based, at least in part, on the policy. The policy may also restrict or promote selection of certain established end-to-end connection(s) via the interface provided. The selected and established end-to-end connection(s) are used for transmitting and receiving data packets.
    Type: Application
    Filed: October 30, 2020
    Publication date: April 15, 2021
    Applicant: Pismo Labs Technology Limited
    Inventors: Patrick Ho Wai SUNG, Ho Ming CHAN, Kit Wai CHAU, Min-Fu TSAI
  • Patent number: 10973354
    Abstract: An illuminable decoration comprises at least two trunk sections, each trunk section includes a hollow tube and a cable assembly coupled to each trunk section. Each cable assembly comprises a first modular electrical connector end that has an inner socket and an outer plug that circumscribes the inner socket. Further, each cable assembly comprises a second modular electrical connector end that has an inner plug and an outer socket that circumscribes the inner plug. A first electrical wire electrically couples between the inner socket of the first modular electrical connector and the inner plug of the second modular electrical connector. Also, a second electrical wire electrically couples between the outer plug of the first modular electrical connector and the outer socket of the second modular electrical connector. When two trunk sections are assembled together end-to-end, the trunk sections are mechanically and electrically coupled to form a modular electrical distribution system.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: April 13, 2021
    Inventor: Chang Fu Tsai
  • Publication number: 20210098386
    Abstract: An electronic device and a manufacturing method thereof are provided. The method includes at least the following steps. An insulating encapsulant is formed to encapsulate a multi-layered structure and a semiconductor die, where the multi-layered structure includes a first conductor, a diffusion barrier layer on the first conductor, and a metallic layer on the diffusion barrier layer, and the insulating encapsulant at least exposes a portion of the semiconductor die and a portion of the first conductor. A redistribution structure is formed over the insulating encapsulant, the semiconductor die, and the first conductor. The metallic layer is removed to form a recess in the insulating encapsulant. A second conductor is formed in the recess over the diffusion barrier layer, where the first conductor, the diffusion barrier layer, and the second conductor form a conductive structure that is electrically coupled to the semiconductor die through the redistribution structure.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Hou-Ju Huang, Shih-Ting Lin, Szu-Wei Lu, Hung-Wei Tsai
  • Patent number: 10964037
    Abstract: An optical projector module to establish distance to target object in a field of view for three dimensional image acquisition purposes includes a printed circuit board, point light sources mounted on the printed circuit board to emit a plurality of light beams, a lens unit apart from the plurality of point light sources, and a distance adjusting unit connected to the lens unit. A memory storage device is also included. The lens unit comprises separated lenses, the adjusting unit can adjust distances between the lenses of the lens unit, and light beams with a number of light spot patterns can accordingly be projected. Previously-captured images in the memory storage device can be referred to in seeking target objects in the field of view and light beams in different spot-concentrations on or around the target object enable calculations for the capture of images in three dimensions of the target object.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: March 30, 2021
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Yu-Yang Chih, Ming-Fu Tsai, Hsueh-Feng Hsu
  • Publication number: 20210091005
    Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die, a semiconductor bridge, an integrated passive device, a first redistribution layer, and connective terminals. The second semiconductor die is disposed beside the first semiconductor die. The semiconductor bridge electrically connects the first semiconductor die with the second semiconductor die. The integrated passive device is electrically connected to the first semiconductor die. The first redistribution layer is disposed over the semiconductor bridge. The connective terminals are disposed on the first redistribution layer, on an opposite side with respect to the semiconductor bridge. The first redistribution layer is interposed between the integrated passive device and the connective terminals.
    Type: Application
    Filed: March 2, 2020
    Publication date: March 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hsuan Tsai, Chin-Chuan Chang, Szu-Wei Lu, Tsung-Fu Tsai
  • Patent number: 10957687
    Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the semiconductor substrate. A first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and spaced apart from the first and second conductive pads. A first ESD protection element is electrically coupled between the first and second conductive pads. A first device under test (DUT) is electrically coupled between the first and third conductive pads.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jen-Chou Tseng, Ming-Fu Tsai, Tzu-Heng Chang
  • Publication number: 20210082743
    Abstract: Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Inventors: Alexander Kalnitsky, Jen-Chou Tseng, Chia-Wei Hsu, Ming-Fu Tsai
  • Publication number: 20210082906
    Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 18, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin PENG, Li-Wei CHU, Ming-Fu TSAI, Jam-Wem LEE, Yu-Ti SU
  • Publication number: 20210066211
    Abstract: A package structure includes a circuit substrate and a semiconductor package. The semiconductor package is disposed on the circuit substrate, and includes a plurality of semiconductor dies, an insulating encapsulant and a connection structure. The insulating encapsulant comprises a first portion and a second portion protruding from the first portion, the first portion is encapsulating the plurality of semiconductor dies and has a planar first surface, and the second portion has a planar second surface located at a different level than the planar first surface. The connection structure is located over the first portion of the insulating encapsulant on the planar first surface, and located on the plurality of semiconductor dies, wherein the connection structure is electrically connected to the plurality of semiconductor dies and the circuit substrate.
    Type: Application
    Filed: May 4, 2020
    Publication date: March 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Fu Tsai, Kung-Chen Yeh, Li-Chung Kuo, Szu-Wei Lu, Ying-Ching Shih
  • Publication number: 20210066287
    Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 4, 2021
    Inventors: Ming-Fu TSAI, Tzu-Heng CHANG, Yu-Ti SU, Kai-Ping HUANG
  • Patent number: 10923438
    Abstract: A package structure and method for forming the same are provided. The method includes forming a through substrate via structure in a substrate, and forming a first trench in the substrate. The method includes stacking a first stacked die package structure over the substrate using a plurality of first bonding structures. The first bonding structures are between the substrate and the first stacked die package structure, and a there is plurality of cavities between two adjacent first bonding structures. The method also includes forming an underfill layer over the first stacked die package structure and in the cavities, and the underfill layer is formed in a portion of the first trench. The method further includes forming a package layer over the underfill layer.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Fu Tsai, Kung-Chen Yeh, I-Ting Huang, Shih-Ting Lin, Szu-Wei Lu
  • Publication number: 20200395864
    Abstract: An isolated switched-mode power converter converts power from an input source into power for an output load. A digital controller senses a secondary-side voltage, such as a rectified voltage, of the power converter. The secondary-side voltage is divided down using a high-impedance voltage divider. The resultant divided-down voltage is provided to a voltage sensor within the digital controller. The voltage sensor level shifts the provided voltage, and buffers the resulting level-shifted voltage. The buffered, level-shifted voltage is provided to a tracking analog-to-digital converter (ADC) for digitization. The buffered signal provided to the tracking ADC has a high current capability, such that the voltage input to the tracking ADC may quickly converge before the tracking ADC outputs a digital value for the sensed secondary-side voltage.
    Type: Application
    Filed: September 1, 2020
    Publication date: December 17, 2020
    Inventors: Sujata Sen, Ronald Hulfachor, Sue Perranoski, Cha-Fu Tsai
  • Patent number: 10867919
    Abstract: An electronic device and the manufacturing method thereof are provided. The electronic device includes a semiconductor die, a conductive structure electrically coupled to the semiconductor die, an insulating encapsulant encapsulating the semiconductor die and the conductive structure, and a redistribution structure disposed on the insulating encapsulant and the semiconductor die. The conductive structure includes a first conductor, a second conductor, and a diffusion barrier layer between the first conductor and the second conductor. The redistribution structure is electrically connected to the semiconductor die and the first conductor of the conductive structure.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Hou-Ju Huang, Shih-Ting Lin, Szu-Wei Lu, Hung-Wei Tsai
  • Patent number: 10862972
    Abstract: A method and system for transmitting and receiving data packets between two network nodes via one or more end-to-end connections. An interface is provided for selecting one or more possible end-to-end connection(s) or established end-to-end connection(s). The method and system may further comprise receiving a policy, wherein one or more selected end-to-end connections are established based, at least in part, on the policy. The policy may also restrict or promote selection of certain established end-to-end connection(s) via the interface provided. The selected and established end-to-end connection(s) are used for transmitting and receiving data packets.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: December 8, 2020
    Assignee: Pismo Labs Technology Limited
    Inventors: Patrick Ho Wai Sung, Ho Ming Chan, Kit Wai Chau, Min-Fu Tsai