Abstract: A reflective exposure apparatus includes a platform, an illuminating system, a photomask, a chip, and a reflecting convex mirror. The photomask is formed on the platform and faces the illuminating system. The chip is formed on the platform. The illuminating system and the reflecting curved mirror are formed on opposite sides of the platform. The platform can be moved relative to the illuminating system and the reflecting curved mirror.

Abstract: An improved shoelace has an elastic inner core having a plurality of elastic members and a woven string covering the elastic inner layer. The woven string has a plurality of narrow sections and wide sections evenly disposed on two ends of the elastic inner core. Each narrow section wraps around the elastic inner core, each wide section is longer than each narrow section and separated from the elastic inner core. When the elastic inner core is not pulled, the wide sections overlap and fold onto the elastic inner core 10 and has a cone shape with at least three times thickness than the narrow section. When the elastic inner core is pulled, the wide sections are stretched straight.

Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the substrate, and a first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and is spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and is spaced apart from the first and second conductive pads. A fourth conductive pad is disposed over the interconnect structure and is spaced apart from the first, second, and third conductive pads. A first ESD protection element is electrically coupled between the first and second pads; and a second ESD protection element is electrically coupled between the third and fourth pads. A first device under test is electrically coupled between the first and third conductive pads; and a second device under test is electrically coupled between the second and fourth pads.

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first chip, a redistribution layer structure, a plurality of connection pads, a plurality of dummy patterns, a plurality of micro-bumps, a second chip and an underfill layer. The redistribution layer structure is electrically connected to the first chip. The connection pads are electrically connected to the redistribution layer structure. The dummy patterns are at one side of the connection pads. The micro-bumps are electrically connected to the connection pads. The second chip is electrically connected to the micro-bumps. The underfill layer covers the plurality of dummy patterns and surrounds the micro-bumps.

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first chip, a redistribution layer structure, a plurality of connection pads, a plurality of dummy patterns, a plurality of micro-bumps, a second chip and an underfill layer. The redistribution layer structure is electrically connected to the first chip. The connection pads are electrically connected to the redistribution layer structure. The dummy patterns are at one side of the connection pads. The micro-bumps are electrically connected to the connection pads. The second chip is electrically connected to the micro-bumps. The underfill layer covers the plurality of dummy patterns and surrounds the micro-bumps.

Abstract: An optical cover is provided for combining with each lighting unit of a light string and includes a cover body and a mounting member. The cover body is provided on an external surface thereof with a sleeve, in which a through hole is formed for receiving and holding the lighting unit therein. The sleeve is provided with, on opposite sides thereof, with notches that receive extension of an electrical cable of the light string therethrough. The mounting member is mountable to the sleeve of the cover body to fix the lighting unit in the through hole and also fix the electrical cable in the notches. In this way, a user is allowed to select and arrange optical covers of different colors for respectively mounting to multiple lighting units of the light string.

Abstract: Methods and apparatus for processing DNS request in a gateway with WAN and LAN interfaces. The gateway receives a first DNS request from a host via the LAN interface. The gateway selects DNS servers according to predefined selection policies and selects access networks that are authorized to send new DNS requests. The new DNS requests and the first DNA request have the same content. The gateway transmits the new DNS requests to corresponding DNS sever of the selected access networks through the selected access networks and via the WAN interfaces that are connected to the selected access networks. The gateway then identifies valid DNS responses from DNS responses received from the corresponding DNS server. The gateway selects one of the identified valid DNS responses and generates a first new DNS response with the same content thereof. The gateway sends the first new DNS response to the host.

Abstract: Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.

Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.

Abstract: A method and system for processing Domain Name Services (DNS) request in a gateway. The gateway receives a DNS request from a host from its local area network. The gateway then selects DNS server(s) and transmits a new DNS request to at least one DNS server(s). DNS server(s) may or may not be accessible through a first tunnel. The contents of the new DNS request are the same as the content of the received DNS request. Further, when the gateway receives a DNS response corresponding to the DNS request, it determines a decision whether to transfer data to the host whose IP address is specified in the DNS response through a second tunnel. The decision may be based on a geographical location of an IP address.

Abstract: According to an embodiment, a semiconductor device is provided. The device includes a second region having a greater curvature than a first region. The device includes an epitaxy layer of a first conductivity type, a well of a second conductivity type in the epitaxy layer, a drain in the epitaxy layer, a source in the well, and a bulk in the well and in contact with the source, the bulk having a greater area in the second region than in the first region.

Abstract: A disclosed insert for a circular-shaped petri dish can generate a substantially uniform electric field across the petri dish that is filled with a fluid establishing a salt bridge. The insert includes a circular-shaped bottom plate defining a circular-shaped space; a side channel vertically erecting from a circular periphery of said bottom plate; and a pair of current rectifying chambers each having a generally planar shape communicating with the side channel. In at least some aspects of the invention, portions of the side channel bridging the pair of current rectifying chambers each have a generally concave top profile having a lowest point at the center between the pair of current rectifying chambers such that, when the salt bridge is established, the circular-shaped space defined by the bottom plate exhibits a substantially uniform electric field in a substantially entire area of the space.

Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.

Abstract: An energy management strategy for boats and ships is provided. The aforementioned strategy comprises a strategy for low-load conditions and a strategy for high-load conditions, specifically for the sailing conditions of boats and ships. The output and distribution of energy are dynamically adjusted in accordance with commands, tides, time, locations, weather, hydrologic conditions and other factors may impact the sailing, in order to optimize the energy efficiency of boats and ships.

Abstract: A method and structure of improving the robustness of an electrostatic discharge (ESD) protection device is disclosed. One aspect of the instant disclosure provides a semiconductor structure that comprises: a first well structure; a second well structure arranged adjacent to the isolation structure in the substrate, a diffusion region respectively disposed in the first and the second well structures; an isolation structure arranged between the well structures and laterally separating the diffusion regions; and a partition structure arranged in the isolation structure. The partition structure affects a steeper slope on a lateral surface of the isolation structure bordering at least one of the diffusion regions, thereby modifying a ballasting characteristic of the isolation structure.

Abstract: An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.

Abstract: A voice control device includes a microphone module, a voice encoding module, a display and a processing unit. The voice encoding module is electrically connected to the microphone module. The processing unit is electrically connected to the voice encoding module and the display. The microphone module receives a voice signal and transmits the received voice signal to the voice encoding module. One of the voice encoding module and the processing unit analyzes and processes the voice signal to determine a sound source direction of the voice signal and obtains response information according to the voice signal. The processing unit controls the display to rotate to the sound source direction and transmits the response information to the display for displaying the response information.

Abstract: A chip includes a first group of dummy bumps disposed at a top surface of the chip in a first corner of the chip, a second group of dummy bumps disposed at the top surface of the chip in a second corner of the chip, and active bump connectors disposed at the top surface of the chip. The chip also includes an outer seal ring disposed around a periphery of the chip, a first seal ring arrangement disposed around the first group of dummy bumps, and a second seal ring arrangement disposed around the second group of dummy bumps. The first seal ring arrangement and second seal ring arrangement are disposed in dielectric layers underlying the first and second groups of dummy bumps.

Abstract: A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface.