Patents by Inventor Fu Tsai

Fu Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated Circuit Packages and Methods for Forming the Same
    Publication number: 20180308778
    Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.
    Type: Application
    Filed: June 29, 2018
    Publication date: October 25, 2018
    Inventors: Chia-Wei Tu, Hsien-Wei Chen, Tsung-Fu Tsai, Wen-Hsiung Lu, Yian-Liang Kuo
  • METHODS AND SYSTEMS FOR PROCESSING A DNS REQUEST
    Publication number: 20180262461
    Abstract: A method and system for processing Domain Name Services (DNS) request in a gateway. The gateway receives a DNS request from a host from its local area network. The gateway then selects DNS server(s) and transmits a new DNS request to at least one DNS server(s). DNS server(s) may or may not be accessible through a first tunnel. The contents of the new DNS request are the same as the content of the received DNS request. Further, when the gateway receives a DNS response corresponding to the DNS request, it determines a decision whether to transfer data to the host whose IP address is specified in the DNS response through a second tunnel. The decision may be based on a geographical location of an IP address.
    Type: Application
    Filed: March 5, 2018
    Publication date: September 13, 2018
    Applicant: Pismo Labs Technology Limited
    Inventors: Alex Wing Hong Chan, Ho Ming Chan, Kit Wai Chau, Chi Pan Yip, Min-Fu Tsai
  • Ultra high voltage device
    Patent number: 10074745
    Abstract: According to an embodiment, a semiconductor device is provided. The device includes a second region having a greater curvature than a first region. The device includes an epitaxy layer of a first conductivity type, a well of a second conductivity type in the epitaxy layer, a drain in the epitaxy layer, a source in the well, and a bulk in the well and in contact with the source, the bulk having a greater area in the second region than in the first region.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ming-Fu Tsai, Yu-Ti Su, Jen-Chou Tseng
  • 3D POLYMERIC INSERT TO APPLY UNIFORM ELECTRIC FIELD IN CIRCULAR CULTUREWARE
    Publication number: 20180251717
    Abstract: A disclosed insert for a circular-shaped petri dish can generate a substantially uniform electric field across the petri dish that is filled with a fluid establishing a salt bridge. The insert includes a circular-shaped bottom plate defining a circular-shaped space; a side channel vertically erecting from a circular periphery of said bottom plate; and a pair of current rectifying chambers each having a generally planar shape communicating with the side channel. In at least some aspects of the invention, portions of the side channel bridging the pair of current rectifying chambers each have a generally concave top profile having a lowest point at the center between the pair of current rectifying chambers such that, when the salt bridge is established, the circular-shaped space defined by the bottom plate exhibits a substantially uniform electric field in a substantially entire area of the space.
    Type: Application
    Filed: September 16, 2016
    Publication date: September 6, 2018
    Applicant: OKINAWA INSTITUTE OF SCIENCE AND TECHNOLOGY SCHOOL CORPORATION
    Inventors: Hsieh-Fu TSAI, Amy Shen FRIED, Ji-Yen CHENG
  • Integrated circuit packages and methods for forming the same
    Patent number: 10056312
    Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: August 21, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Tu, Hsien-Wei Chen, Tsung-Fu Tsai, Wen-Hsiung Lu, Yian-Liang Kuo
  • Energy management strategy for boats and ships
    Patent number: 10046651
    Abstract: An energy management strategy for boats and ships is provided. The aforementioned strategy comprises a strategy for low-load conditions and a strategy for high-load conditions, specifically for the sailing conditions of boats and ships. The output and distribution of energy are dynamically adjusted in accordance with commands, tides, time, locations, weather, hydrologic conditions and other factors may impact the sailing, in order to optimize the energy efficiency of boats and ships.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: August 14, 2018
    Assignee: SHIP AND OCEAN INDUSTRIES R&D CENTER
    Inventors: Chih-Hung Lin, Hung-Hsi Lin, Sheng-Hua Chen, Jen-Fu Tsai, Hsiao-Yu Hsu, Shean-Kwang Chou, Kai-Ping Hsu
  • Structure and method for enhancing robustness of ESD device
    Patent number: 10026640
    Abstract: A method and structure of improving the robustness of an electrostatic discharge (ESD) protection device is disclosed. One aspect of the instant disclosure provides a semiconductor structure that comprises: a first well structure; a second well structure arranged adjacent to the isolation structure in the substrate, a diffusion region respectively disposed in the first and the second well structures; an isolation structure arranged between the well structures and laterally separating the diffusion regions; and a partition structure arranged in the isolation structure. The partition structure affects a steeper slope on a lateral surface of the isolation structure bordering at least one of the diffusion regions, thereby modifying a ballasting characteristic of the isolation structure.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: July 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Alexander Kalnitsky, Jen-Chou Tseng, Chia-Wei Hsu, Ming-Fu Tsai
  • Integrated circuit with multi-level arrangement of e-fuse protected decoupling capacitors
    Patent number: 10014252
    Abstract: An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry has a first power node and a second power node. The first capacitor is coupled to the first fuse serially to form a first segment. The second capacitor is coupled to the second fuse serially to form a second segment. The first segment and the second segment are coupled together in parallel and between the first power node and the second power node.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: July 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Cheng Chang, Liang-Chen Lin, Fu-Tsai Hou, Tung-Chin Yeh, Shih-Kai Lin, Gia-Her Lu, Jyun-Lin Wu, Hsien-Pin Hu
  • VOICE CONTROL DEVICE, SYSTEM, AND METHOD THEREOF
    Publication number: 20180174584
    Abstract: A voice control device includes a microphone module, a voice encoding module, a display and a processing unit. The voice encoding module is electrically connected to the microphone module. The processing unit is electrically connected to the voice encoding module and the display. The microphone module receives a voice signal and transmits the received voice signal to the voice encoding module. One of the voice encoding module and the processing unit analyzes and processes the voice signal to determine a sound source direction of the voice signal and obtains response information according to the voice signal. The processing unit controls the display to rotate to the sound source direction and transmits the response information to the display for displaying the response information.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 21, 2018
    Inventors: YU-YANG CHIH, MING-CHUN HO, MING-FU TSAI, CHENG-PING LIU, FU-BIN WANG, SHIH-LUN LIN
  • Packaging Structures of Integrated Circuits
    Publication number: 20180151528
    Abstract: A chip includes a first group of dummy bumps disposed at a top surface of the chip in a first corner of the chip, a second group of dummy bumps disposed at the top surface of the chip in a second corner of the chip, and active bump connectors disposed at the top surface of the chip. The chip also includes an outer seal ring disposed around a periphery of the chip, a first seal ring arrangement disposed around the first group of dummy bumps, and a second seal ring arrangement disposed around the second group of dummy bumps. The first seal ring arrangement and second seal ring arrangement are disposed in dielectric layers underlying the first and second groups of dummy bumps.
    Type: Application
    Filed: January 26, 2018
    Publication date: May 31, 2018
    Inventors: Tsung-Fu Tsai, Chia-Wei Tu, Yian-Liang Kuo, Ru-Ying Huang
  • Isolation rings for packages and the method of forming the same
    Patent number: 9929070
    Abstract: A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: March 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Horng Chang, Tin-Hao Kuo, Tsung-Fu Tsai, Min-Feng Ku
  • Out-of-band retrieval of network interface controller information
    Patent number: 9921852
    Abstract: In some implementations, network interface controller (NIC) configuration information can be obtained from a NIC prior to booting up an operating system. For example, a Basic Input Output System (BIOS) can obtain the NIC configuration information from the NIC during the execution of a system check (e.g., Power-On Self-Test). A system controller can receive the NIC configuration information from the BIOS. The system controller can store the NIC configuration information in memory associated with the system controller. A management system can request the NIC configuration information from the system controller using an out-of-band communication channel. For example, the management system can send the request for NIC configuration information to the system controller prior to powering on a server using a dedicated network interface of the system controller.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: March 20, 2018
    Assignee: QUANTA COMPUTER INC.
    Inventors: Hung-Lu Chu, Chin-Fu Tsai, Yung-Fu Li
  • Methods and systems for processing a DNS request
    Patent number: 9912630
    Abstract: A method and system for processing Domain name Services (DNS) request in a gateway. The gateway receives a DNS request from a host from its local area network. The gateway then selects DNS server(s) and transmits a new DNS request to at least one DNS server(s). DNS server(s) may or may not be accessible through a first tunnel. The contents of the new DNS request are the same as the content of the received DNS request. Further, when the gateway receives a DNS response corresponding to the DNS request, it determines a decision whether to transfer data to the host whose IP address is specified in the DNS response through a second tunnel. The decision may be based on a geographical location of an IP address.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: March 6, 2018
    Assignee: PISMO LABS TECHNOLOGY LTD.
    Inventors: Alex Wing Hong Chan, Ho Ming Chan, Kit Wai Chau, Chi Pan Yip, Min-Fu Tsai
  • Integrated Circuit Packages and Methods for Forming the Same
    Publication number: 20180025959
    Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.
    Type: Application
    Filed: October 2, 2017
    Publication date: January 25, 2018
    Inventors: Chia-Wei Tu, Hsien-Wei Chen, Tsung-Fu Tsai, Wen-Hsiung Lu, Yian-Liang Kuo
  • LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20180012929
    Abstract: A light-emitting device comprises a carrier; a first semiconductor element formed on the carrier and comprising a first semiconductor structure and a second semiconductor structure, wherein the second semiconductor structure is closer to the carrier than the first semiconductor structure is, the first semiconductor structure comprises a first active layer emitting a first light having a first dominant wavelength during a normal operation, and the second semiconductor structure comprises a second active layer; and a bridge on a side surface of the second active layer of the second semiconductor structure.
    Type: Application
    Filed: September 21, 2017
    Publication date: January 11, 2018
    Inventors: Shao-Ping LU, Yi-Ming CHEN, Yu-Ren PENG, Chun-Yu LIN, Chun-Fu TSAI, Tzu-Chieh HSU
  • SHOELACE
    Publication number: 20170367442
    Abstract: An improved shoelace has an elastic inner core having a plurality of elastic members and a woven string covering the elastic inner layer. The woven string has a plurality of narrow sections and wide sections evenly disposed on two ends of the elastic inner core. Each narrow section wraps around the elastic inner core, each wide section is longer than each narrow section and separated from the elastic inner core. When the elastic inner core is not pulled, the wide sections overlap and fold onto the elastic inner core 10 and has a cone shape with at least three times thickness than the narrow section. When the elastic inner core is pulled, the wide sections are stretched straight.
    Type: Application
    Filed: May 8, 2017
    Publication date: December 28, 2017
    Inventors: CHUNG-YANG TSAI, CHING-FU TSAI
  • Color Filter Array and Manufacturing Method thereof
    Publication number: 20170366786
    Abstract: A color filter array for an image sensing device includes a plurality of pixels, for generating a plurality of pixel data of an image; and a control unit, for controlling the plurality of pixels; wherein each of the plurality of pixels is divided into a plurality of sub-pixels; wherein the pixel data outputted by each of the plurality of pixels is generated based on at least one pixel value of the plurality of sub-pixels and the outputted pixel data is smaller than a saturated threshold; wherein at least one pixel in the plurality of pixels has a mixed color by having different sub-pixel colors in the plurality of sub-pixels.
    Type: Application
    Filed: September 5, 2017
    Publication date: December 21, 2017
    Inventors: Wei Hsu, Shen-Fu Tsai, I-Hsiu Chen
  • VIRTUAL CHASSIS MANAGEMENT CONTROLLER
    Publication number: 20170364375
    Abstract: A system for chassis management includes a plurality of motherboards of a chassis, a plurality of baseboard management controllers (BMCs), and at least one chassis level component. Each of the plurality of BMCs is associated with one of the plurality of motherboards. The plurality of BMCs are interconnected via a first communication bus. The plurality of BMCs and the at least one chassis level component are interconnected via a second communication bus. One BMC of the plurality of BMCs is configured to operate as a virtual chassis management controller (VCMC) for the chassis. The VCMC is configured to exchange data with other BMCs of the plurality of BMCs over the first communication bus and manage the at least one chassis level component over the second communication bus.
    Type: Application
    Filed: June 16, 2016
    Publication date: December 21, 2017
    Inventors: Kai-Fan KU, Chin-Fu TSAI
  • VOLTAGE DETECTOR CIRCUITS AND METHODS
    Publication number: 20170346479
    Abstract: A voltage detector includes a first node configured to have a first supply voltage, a second node configured to have a second supply voltage, and an output node. The voltage detector is configured to drive the output node to the first supply voltage in response to a difference between the first supply voltage and the second supply voltage exceeding a predetermined threshold voltage value.
    Type: Application
    Filed: March 6, 2017
    Publication date: November 30, 2017
    Inventors: Ming-Fu TSAI, Jen-Chou TSENG, Kuo-Ji CHEN, Tzu-Heng CHANG
  • Light-emitting device and manufacturing method thereof
    Patent number: 9825088
    Abstract: A light-emitting device comprises a carrier; and a first semiconductor element comprising a first semiconductor structure and a second semiconductor structure, wherein the second semiconductor structure is closer to the carrier than the first semiconductor structure is to the carrier, the first semiconductor structure comprises a first MQW structure configured to emit a first light having a first dominant wavelength during normal operation, and the second semiconductor structure comprises a second MQW structure configured not to emit light during normal operation.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: November 21, 2017
    Assignee: EPISTAR CORPORATION
    Inventors: Shao-Ping Lu, Yi-Ming Chen, Yu-Ren Peng, Chun-Yu Lin, Chun-Fu Tsai, Tzu-Chieh Hsu