Abstract: A mobile terminal device executes an OS including a printing system that supports a first search protocol and a printing function using a first printing method as a standard. If instructions for the use of the printing system included in the OS are provided by the user, the mobile terminal device receives a message conforming to the first search protocol from a printer that has been newly detected via the first search protocol. In a case where the detected printer has been selected, if the printer is determined not to conform to the first printing method based on the contents of the received message, the mobile terminal device activates a function for downloading a plug-in that supports the printer.

Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.

Abstract: According to one embodiment, a semiconductor memory device includes first to third conductive layers extending along a first direction, and a memory portion. A portion of the second conductive layer is provided between the third conductive layer and a portion of the first conductive layer. The first conductive layer includes a first end portion crossing the first direction. The second conductive layer includes a second end portion crossing the first direction. The third conductive layer includes a third end portion crossing the first direction. A position in the first direction of a portion of the second end portion is between a position of the first end portion and a position of the third end portion. The position in the first direction of the portion of the second end portion is between a position of another portion of the second end portion and the position of the third end portion.

Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.

Abstract: According to one embodiment, a semiconductor memory device includes first to third conductive layers extending along a first direction, and a memory portion. A portion of the second conductive layer is provided between the third conductive layer and a portion of the first conductive layer. The first conductive layer includes a first end portion crossing the first direction. The second conductive layer includes a second end portion crossing the first direction. The third conductive layer includes a third end portion crossing the first direction. A position in the first direction of a portion of the second end portion is between a position of the first end portion and a position of the third end portion. The position in the first direction of the portion of the second end portion is between a position of another portion of the second end portion and the position of the third end portion.

Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.

Abstract: An inductor component includes a core base material, a magnetic body in the core, a first conductor pattern formed on primary surface of the core, a second conductor pattern formed on secondary surface of the core, and through-hole conductors formed in through holes through the core such that the conductors are connecting the first and second patterns. The first pattern, second pattern and conductors are positioned to form an inductor such that the magnetic body is positioned on inner side of the inductor, each conductor has a diameter k1, each pattern has conductor thickness in range of 50 ?m to 200 ?m and has line patterns each having width w1 and separated by line separation distance w2, and a ratio of cross-sectional area of each line pattern to cross-sectional area of each conductor along the diameter k1 in direction of the width w1 is in range of 0.8 to 2.0.

Abstract: An embodiment includes: a semiconductor substrate, a memory cell array region including a plurality of conductive layers connected to memory cells arranged in a stacking direction on the semiconductor substrate; a peripheral region including a transistor on the substrate; a plurality of first layers and second layers stacked alternately in the stacking direction, above the transistor; and a plurality of first contacts penetrating the plurality of first and second layers and connected to the transistor. The plurality of first layers and second layers are stacked alternately in the stacking direction, above the transistor disposed in the peripheral region. A plurality of contacts penetrating the plurality of first layers and second layers are connected to the transistor. Moreover, the first layer mainly contains a different material from the second layer.

Abstract: An information processing apparatus instructs a plurality of print plug-ins having at least a printer search function to search for a printer and displays, if the plurality of print plug-ins are instructed to perform the search, a first screen which includes (1) a printer detected by search processing performed by the plurality of print plug-ins instructed to perform the search and includes (2) an object for shifting to a second screen but does not include (3) a link to a download page of a print plug-in that is not installed, and displays, in response to an instruction given to the object in the first screen, the second screen which includes (3) the link to the download page of the print plug-in that is not installed.

Abstract: Information on a peripheral device in short distance wireless communication is obtained, it is determined whether the information contains an address of the peripheral device, and peripheral devices on a network is searched for if it is determined that the information does not contain the address of the peripheral device.

Abstract: The memory cell array includes a memory string and a select transistor. The memory string includes plural memory cells connected in series, the memory string being formed to extend in a first direction as a lengthwise direction. The select transistor is connected to one end of the memory string. In the wiring section, a conductive layer and an interlayer insulating layer are laminated alternately to form plural layers. The conductive layer functions as a gate electrode of the memory cells and the select transistor. One select transistor includes plural conductive layers, and the plural conductive layers are connected in common by a common first contact. The plurality of the conductive layers and the first contact include a barrier metal formed in a periphery thereof. The plurality of the conductive layers and the first contact are in contact without the barrier metal therebetween at a boundary thereof.

Abstract: An embodiment includes: a semiconductor substrate, a memory cell array region including a plurality of conductive layers connected to memory cells arranged in a stacking direction on the semiconductor substrate; a peripheral region including a transistor on the substrate ; a plurality of first layers and second layers stacked alternately in the stacking direction, above the transistor; and a plurality of first contacts penetrating the plurality of first and second layers and connected to the transistor. The plurality of first layers and second layers are stacked alternately in the stacking direction, above the transistor disposed in the peripheral region. A plurality of contacts penetrating the plurality of first layers and second layers are connected to the transistor. Moreover, the first layer mainly contains a different material from the second layer.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a first stacked body; a second stacked body being larger in number of stacked layers than the first stacked body, the second stacked body including a plurality of electrode layers separately stacked each other; a third stacked body being smaller in number of stacked layers than the first stacked body. The first stacked body includes a plurality of first layers separately stacked each other, and a plurality of second layers provided between the first layers. The third stacked body includes a third layer including a same material as the material of the first layers, and a fourth layer including a same material as the material of the second layers.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction. Ends of the first conductive layers and ends of the third conductive layers are formed in shapes of steps extending in the first direction and ends of the second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.

Abstract: An information processing apparatus manages whether each of a plurality of print plug-ins is in an enabled state or in a disabled state, the plurality of print plug-ins adding at least a search function to an operating system operating on the information processing apparatus, and, if a search for a printer is instructed and the plurality of print plug-ins includes a print plug-in in the disabled state, performs a search for a printer by a print plug-in in the enabled state, and displays a detection result and a setting screen for setting the print plug-in in the disabled state to the enabled state.

Abstract: When an application is launched, it is determined whether a launching source is a device management. If it is determined that the launching source is the device management, a peripheral apparatus associated with the device management serving as the launching source is controlled as a default peripheral apparatus.

Abstract: The memory cell array includes a memory string and a select transistor. The memory string includes plural memory cells connected in series, the memory string being formed to extend in a first direction as a lengthwise direction. The select transistor is connected to one end of the memory string. In the wiring section, a conductive layer and an interlayer insulating layer are laminated alternately to form plural layers. The conductive layer functions as a gate electrode of the memory cells and the select transistor. One select transistor includes plural conductive layers, and the plural conductive layers are connected in common by a common first contact. The plurality of the conductive layers and the first contact include a barrier metal formed in a periphery thereof. The plurality of the conductive layers and the first contact are in contact without the barrier metal therebetween at a boundary thereof.

Abstract: A printed wiring board includes a core substrate including resin and inorganic fiber, a first buildup layer formed on a first surface of the substrate and including resin insulating layers and first conductive layers, and a second buildup layer formed on a second surface of the substrate on the opposite side of the core substrate with respect to the first surface and including resin insulating layers and second conductive layers. The first conductive layers in the first buildup have sum V1 of volumes which is greater than sum V2 of volumes of the second conductive layers in the second buildup, and the substrate has a first-surface side portion which has resin amount greater than resin amount of a second-surface side portion of the substrate where boundary between the first-surface and second-surface side portions is set with respect to the center line in the thickness direction of the substrate.

Abstract: An electronic key registration system includes a controller of a communication subject, an initial electronic key that communicates with the communication subject and has an initial encryption key generation code, an additional electronic key that communicates with the communication subject, and an information center including an additional encryption key. The initial electronic key holds an initial encryption key generated from the initial encryption key generation code and a logic. The controller holds the logic and identification information of the communication subject. The controller acquires the initial encryption key generation code from the initial electronic key, generates an initial encryption key from the initial encryption key generation code and the logic held by the controller, and stores the initial encryption key. The information center sends the additional encryption key to the additional electronic key or the controller through a network.

Abstract: Information on a peripheral device in short distance wireless communication is obtained, it is determined whether the information contains an address of the peripheral device, and peripheral devices on a network is searched for if it is determined that the information does not contain the address of the peripheral device.