Patents by Inventor Hisashi Kato

Hisashi Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200083769
    Abstract: A coil substrate for a motor includes a flexible substrate, and multiple coils formed on a surface of the flexible substrate. Each of the coils has a wiring having first wiring portions and second wiring portions extending from the first wirings respectively and is formed such that the first wiring portions extend parallel with respect to each other and that the second wiring portions extend not parallel to the first wirings, and the flexible substrate is formed to be formed around a magnet of a motor such that the first wiring portions form an angle that is substantially perpendicular to a rotation direction of the motor.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 12, 2020
    Applicant: IBIDEN CO., LTD.
    Inventors: Haruhiko MORITA, Hitoshi MIWA, Shinobu KATO, Toshihiko YOKOMAKU, Hisashi KATO, Takahisa HIRASWA, Tetsuya MURAKI, Takayuki FURUNO
  • Publication number: 20200075223
    Abstract: A planar transformer includes a flexible insulating substrate having a first surface and a second surface on the opposite side with respect to the first surface, and multiple coils formed side by side on the first surface and the second surface of the flexible insulating substrate such that each of the coils includes a spiral-shaped wiring. The flexible insulating substrate has bending portions formed such that the flexible insulating substrate is folded at the bending portions and stack the coils one another.
    Type: Application
    Filed: August 29, 2019
    Publication date: March 5, 2020
    Applicant: IBIDEN CO., LTD.
    Inventors: Haruhiko MORITA, Hitoshi MIWA, Shinobu KATO, Toshihiko YOKOMAKU, Hisashi KATO, Takahisa HIRASAWA, Tetsuya MURAKI, Takayuki FURUNO
  • Publication number: 20200076263
    Abstract: A motor coil substrate includes a flexible substrate, and multiple coils formed on the flexible substrate such that each of the coils has a spiral shape. The flexible substrate has multiple folding lines formed and the multiple coils positioned such that the flexible substrate is folded at the folding lines and wound around a magnet and that an m-th coil and an (m+1)-th coil of the coils partially overlap one another when folded at the folding lines.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 5, 2020
    Applicant: IBIDEN CO., LTD.
    Inventors: Haruhiko MORITA, Hitoshi MIWA, Shinobu KATO, Toshihiko YOKOMAKU, Hisashi KATO, Takahisa HIRASAWA, Tetsuya MURAKI, Takayuki FURUNO
  • Publication number: 20200075224
    Abstract: A planar transfoinier includes a flexible insulating substrate having a pair of short sides, a pair of long sides, a first surface, and a second surface on an opposite side with respect to the first surface, multiple coils formed side by side on the first surface and second surface of the flexible insulating substrate such that each of the coils has a spiral-shaped wiring, and multiple terminals formed on the flexible insulating substrate and connected to the coils respectively such that the terminals are positioned in a center portion of the flexible insulating substrate formed close to a center of the long sides of the flexible insulating substrate. The flexible insulating substrate has multiple bending portions formed such that the flexible insulating substrate is folded at the bending portions and stacks the coils one another.
    Type: Application
    Filed: August 29, 2019
    Publication date: March 5, 2020
    Applicant: IBIDEN CO., LTD.
    Inventors: Haruhiko MORITA, Hitoshi MIWA, Shinobu KATO, Toshihiko YOKOMAKU, Hisashi KATO, Takahisa HIRASAWA, Tetsuya MURAKI, Takayuki FURUNO
  • Patent number: 10553600
    Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: February 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Takuya Inatsuka, Tadashi Iguchi, Murato Kawai, Hisashi Kato, Megumi Ishiduki
  • Publication number: 20200025819
    Abstract: An inspection device is provided, which is capable of detecting a short circuit failure even when a connector is provided on a wiring board. The inspection device is configured to inspect a short circuit failure generated at any connected part of a plurality of pins 153 to a wiring board via solder. The plurality of pins 153 is included in a connector provided on the wiring board. The inspection device includes: a wiring 11 connected to certain pins 153 of the plurality of pins 153; a second wiring 12 connected to remaining pins 153 of the plurality of pins 153; and a tester unit connected to the first wiring 11 and to the second wiring 12 so as to inspect insulation between the certain pins 153 and the remaining pins 153.
    Type: Application
    Filed: July 15, 2019
    Publication date: January 23, 2020
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Hisashi KATO
  • Patent number: 10483124
    Abstract: According to one embodiment, a semiconductor device includes: a first stack above a substrate and including insulation layers and conductive layers alternately stacked in a first direction, the first stack including a staircase-shaped portion in an end portion of the first stack in a second direction parallel to a main face of the substrate, the staircase-shaped portion including steps and terraces corresponding to the conductive layers, at least a part of the steps having arc shape curved along a third direction crossing the second direction; and a second stack above the substrate and including first and second layers stacked in the first direction. In the second and/or third direction, a dimension of the first stack is larger than a dimension of the second stack.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: November 19, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masakazu Sawano, Takahiro Tomimatsu, Junichi Shibata, Hideki Inokuma, Hisashi Kato, Kenta Yoshinaga
  • Publication number: 20190303076
    Abstract: A print processing system includes an image processing apparatus configured to execute print processing, and a client apparatus that includes a class driver configured to convert data as a target of the print processing into print data and to transmit a printing command for causing the image processing apparatus to execute the print processing by using a standard function to the image processing apparatus together with the print data, wherein the client apparatus includes an acquisition unit configured to acquire print setting information that specifies a print setting included in the image processing apparatus from the image processing apparatus via the class driver, a display unit configured to display a print setting screen based on the print setting information acquired by the acquisition unit, and a transmission unit configured to transmit the print setting information about a print setting selected by a user on the print setting screen.
    Type: Application
    Filed: March 19, 2019
    Publication date: October 3, 2019
    Inventor: Hisashi Kato
  • Publication number: 20190287903
    Abstract: A semiconductor memory device according to an embodiment includes a substrate; a plate-like first conductivity layer provided above the substrate and extending parallel to a substrate plane to bestride first and second regions; a plate-like second conductivity layer provided above the first conductivity layer to be separated from the first conductivity layer, an end portion of the first conductivity layer has a protruding staircase shape in the first region, the second conductivity layer extending parallel to the first conductivity layer to bestride the first and second regions; a first contact connected to the first conductivity layer at a side surface or a bottom surface of the first conductivity layer and extending from the first conductivity layer toward the substrate, the first contact being connected at a position where the end portion of the first conductivity layer in the first region protrudes, and a diameter size of a portion of the first contact connected at a side surface or a bottom surface of th
    Type: Application
    Filed: August 29, 2018
    Publication date: September 19, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Kenta Yoshinaga, Hideki Inokuma, Hisashi Kato, Masakazu Sawano
  • Patent number: 10388451
    Abstract: An inductor component includes a core base material, a magnetic body in the core, a first conductor pattern formed on primary surface of the core, a second conductor pattern formed on secondary surface of the core, and through-hole conductors formed in through holes through the core such that the conductors are connecting the first and second patterns. The first pattern, second pattern and conductors are positioned to form an inductor such that the magnetic body is positioned on inner side of the inductor, each conductor has a diameter k1, each pattern has conductor thickness in range of 50 ?m to 200 ?m and has line patterns each having width w1 and separated by line separation distance w2, and a ratio of cross-sectional area of each line pattern to cross-sectional area of each conductor along the diameter k1 in direction of the width w1 is in range of 0.8 to 2.0.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: August 20, 2019
    Assignee: IBIDEN CO., LTD.
    Inventors: Yasuhiko Mano, Hiroaki Kodama, Hisashi Kato
  • Publication number: 20190245401
    Abstract: A motor coil substrate includes a flexible insulating substrate having a cylindrical shape, wirings formed on a first surface of the flexible insulating substrate and a second surface of the flexible insulating substrate on the opposite side with respect to the first surface, and via conductors including copper plating penetrating through the flexible insulating substrate such that the via conductors are connecting the wirings formed on the first surface and the wirings formed on the second surface. The wirings and the via conductors form coils formed in spiral shapes, and the flexible insulating substrate is wound more than one turn in a circumferential direction of the cylindrical shape such that the first surface on an inner side of the cylindrical shape and the second surface on an outer side of the cylindrical shape oppose each other.
    Type: Application
    Filed: February 8, 2019
    Publication date: August 8, 2019
    Applicant: IBIDEN CO., LTD.
    Inventors: Haruhiko Morita, Shinobu Kato, Hitoshi Miwa, Hisashi Kato, Toshihiko Yokomaku
  • Publication number: 20190214268
    Abstract: According to one embodiment, a semiconductor device includes: a first stack above a substrate and including insulation layers and conductive layers alternately stacked in a first direction, the first stack including a staircase-shaped portion in an end portion of the first stack in a second direction parallel to a main face of the substrate, the staircase-shaped portion including steps and terraces corresponding to the conductive layers, at least a part of the steps having arc shape curved along a third direction crossing the second direction; and a second stack above the substrate and including first and second layers stacked in the first direction. In the second and/or third direction, a dimension of the first stack is larger than a dimension of the second stack.
    Type: Application
    Filed: September 10, 2018
    Publication date: July 11, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masakazu SAWANO, Takahiro TOMIMATSU, Junichi SHIBATA, Hideki INOKUMA, Hisashi KATO, Kenta YOSHINAGA
  • Publication number: 20190182354
    Abstract: An information processing apparatus instructs a plurality of print plug-ins having at least a printer search function to search for a printer and displays, if the plurality of print plug-ins are instructed to perform the search, a first screen which includes (1) a printer detected by search processing performed by the plurality of print plug-ins instructed to perform the search and includes (2) an object for shifting to a second screen but does not include (3) a link to a download page of a print plug-in that is not installed, and displays, in response to an instruction given to the object in the first screen, the second screen which includes (3) the link to the download page of the print plug-in that is not installed.
    Type: Application
    Filed: February 19, 2019
    Publication date: June 13, 2019
    Inventor: Hisashi Kato
  • Publication number: 20190115130
    Abstract: A laminated coil substrate includes a printed wiring board including a resin substrate, a first conductor layer on first surface of the substrate and including coils, and a second conductor layer formed on second surface of the substrate on the opposite side and including coils. The printed wiring board includes first, second and third coil substrates that are folded such that the second surface of the substrate in the first and second coil substrates oppose each other and that the first surface of the substrate in the second and third coil substrates oppose each other, the second conductor layer of the printed wiring board includes connection wire on the second surface of the substrate and connecting the first and second coil substrates, and the first conductor layer of the printed wiring board includes connection wire on the first surface of the substrate and connecting the second and third coil substrates.
    Type: Application
    Filed: October 16, 2018
    Publication date: April 18, 2019
    Applicant: IBIDEN CO., LTD.
    Inventors: Haruhiko Morita, Shinobu Kato, Hitoshi Miwa, Hisashi Kato, Toshihiko Yokomaku
  • Patent number: 10250719
    Abstract: An information processing apparatus instructs a plurality of print plug-ins having at least a printer search function to search for a printer and displays, if the plurality of print plug-ins are instructed to perform the search, a first screen which includes (1) a printer detected by search processing performed by the plurality of print plug-ins instructed to perform the search and includes (2) an object for shifting to a second screen but does not include (3) a link to a download page of a print plug-in that is not installed, and displays, in response to an instruction given to the object in the first screen, the second screen which includes (3) the link to the download page of the print plug-in that is not installed.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: April 2, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hisashi Kato
  • Publication number: 20190074294
    Abstract: A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction. Ends of the first conductive layers and ends of the third conductive layers are formed in shapes of steps extending in the first direction and ends of the second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.
    Type: Application
    Filed: November 7, 2018
    Publication date: March 7, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Tadashi IGUCHI, Murato Kawai, Toru Matsuda, Hisashi Kato, Megumi Ishiduki
  • Publication number: 20190074745
    Abstract: A motor coil includes a magnet structure, and a laminated coil substrate formed on the magnet structure and including coil substrates and adhesive layers alternately laminated. The coil substrates are formed by folding a printed wiring board including a resin substrate, a first conductor layer formed on a first surface of the resin substrate and forming coils, and a second conductor layer formed on a second surface on the opposite side with respect to the first surface and forming coils, and the adhesive layers include an adhesive layer including a magnetic sheet.
    Type: Application
    Filed: September 7, 2018
    Publication date: March 7, 2019
    Applicant: IBIDEN CO. , LTD.
    Inventors: Haruhiko MORITA, Shinobu KATO, Hitoshi MIWA, Hisashi KATO, Toshihiko YOKOMAKU
  • Patent number: 10199386
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a first stacked body; a second stacked body being larger in number of stacked layers than the first stacked body, the second stacked body including a plurality of electrode layers separately stacked each other; a third stacked body being smaller in number of stacked layers than the first stacked body. The first stacked body includes a plurality of first layers separately stacked each other, and a plurality of second layers provided between the first layers. The third stacked body includes a third layer including a same material as the material of the first layers, and a fourth layer including a same material as the material of the second layers.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: February 5, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Terada, Hisashi Kato, Noriaki Koyama
  • Publication number: 20180374630
    Abstract: A coil includes a resin substrate, a first coil structure formed on a first surface of the resin substrate, a second coil structure formed on a second surface of the resin substrate on the opposite side with respect to the first surface such that the second coil structure is formed at a position corresponding to the first coil structure, a third coil structure formed on the second surface such that the third coil structure is positioned adjacent to the second coil structure, and a fourth coil structure formed on the first surface such that the fourth coil structure is formed at a position corresponding to the third coil structure. The resin substrate is folded such that the second coil structure and the third coil structure oppose each other.
    Type: Application
    Filed: June 27, 2018
    Publication date: December 27, 2018
    Applicant: IBIDEN CO., LTD.
    Inventors: Haruhiko MORITA, Shinobu Kato, Hitoshi Miwa, Hisashi Kato, Toshihiko Yokomaku
  • Patent number: 10147735
    Abstract: A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction. Ends of the first conductive layers and ends of the third conductive layers are formed in shapes of steps extending in the first direction and ends of the second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: December 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tadashi Iguchi, Murato Kawai, Toru Matsuda, Hisashi Kato, Megumi Ishiduki