Patents by Inventor Hsiang Wang

Hsiang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220139652
    Abstract: A manufacture method of a concave disc-shaped structure of bimetal strip, particularly to one that is a coaxial positioning method of the guide hole which having elastic disc-shape structure bimetal strips not affected by external stress, which having a bimetal structure which outer edge will not be damaged and does not affect by stress while inner edge pulling closed to the outer edge, it includes: a bimetal strip, a lug, and an assembling jig, having two displaceable positioning holes, and use the guiding surface to make the two positioning holes gradually turn inside to condense to the combining surface of the lugs, so as to achieve the purpose of accurate positioning and combination.
    Type: Application
    Filed: October 27, 2021
    Publication date: May 5, 2022
    Inventors: YI-HSIANG WANG, I-YING WANG
  • Patent number: 11323237
    Abstract: A repeater and a synchronization method for the same are provided. The synchronization method includes: configuring a base station to transmit an input signal during downlink transmission durations according to a time division duplex (TDD) configuration, in which the TDD configuration defines a predetermined pattern composed of an uplink transmission duration and a downlink transmission duration; configuring a processor generate a received signal code according to the input signal; configuring the processor to sample the received signal code by using a signal window to generate a target pattern; configuring the processor to dynamically compare the target pattern with the predetermined pattern according to the TDD configuration, positions of the received downlink transmission durations and positions of the received uplink transmission durations stored in a memory of the repeater, and determine whether the target pattern matches to the predetermined pattern.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: May 3, 2022
    Assignee: WISTRON NEWEB CORPORATION
    Inventors: Chia-Hsiang Wang, Chieh-Wen Cheng
  • Publication number: 20220108934
    Abstract: A package structure includes a first circuit board, a second circuit board, at least one electronic component, at least one conductive lead, and a molding compound. The first circuit board includes a first circuit layer and a second circuit layer. The second circuit board includes a third circuit layer and a fourth circuit layer. The electronic component is disposed between the first circuit board and the second circuit board. The conductive lead contacts at least one of the second circuit layer and the third circuit layer. The conductive lead has a vertical height, and the vertical height is greater than a vertical distance between the second circuit layer and the third circuit layer. The molding compound covers the first circuit board, the second circuit board, the electronic component, and the conductive lead. The molding compound exposes the first circuit layer and the fourth circuit layer, and the conductive lead extends outside the molding compound.
    Type: Application
    Filed: March 18, 2021
    Publication date: April 7, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: Ra-Min Tain, Po-Hsiang Wang, Chi-Chun Po
  • Patent number: 11288994
    Abstract: A source driver adapted to drive a display panel is provided. The source driver includes an output buffer and a slew rate adjustment circuit. An input terminal of the output buffer receives a driving voltage. An output terminal of the output buffer outputs an output signal adapted to drive the display panel. The slew rate adjustment circuit dynamically adjusts a slew rate of a rising edge of the output signal according to a first setting and dynamically adjusts a slew rate of a falling edge of the output signal according to a second setting independent of the first setting, such that the adjustment to the slew rate of the rising edge of the output signal is independent of the adjustment to the slew rate of the falling edge of the output signal.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: March 29, 2022
    Assignee: Novatek Microelectronics Corp.
    Inventors: Ying-Hsiang Wang, Chia-Lun Chang
  • Publication number: 20220093781
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device. The semiconductor device includes a channel layer disposed over a base substrate, and an active layer disposed on the channel layer. A source contact and a drain contact are over the active layer and are laterally spaced apart from one another along a first direction. A gate electrode is arranged on the active layer between the source contact and the drain contact. A passivation layer is arranged on the active layer and laterally surrounds the source contact, the drain contact, and the gate electrode. A conductive structure is electrically coupled to the source contact and is disposed laterally between the gate electrode and the source contact. The conductive structure extends along an upper surface and a sidewall of the passivation layer.
    Type: Application
    Filed: December 1, 2021
    Publication date: March 24, 2022
    Inventors: Ming-Cheng Lin, Chen-Bau Wu, Chun Lin Tsai, Haw-Yun Wu, Liang-Yu Su, Yun-Hsiang Wang
  • Publication number: 20220095464
    Abstract: A circuit board includes a composite structure layer, at least one conductive structure, a thermally conductive substrate, and a thermal interface material layer. The composite structure layer has a cavity and includes a first structure layer, a second structure layer, and a connecting structure layer. The first structure layer includes at least one first conductive member, and the second structure layer includes at least one second conductive member. The cavity penetrates the first structure layer and the connecting structure layer to expose the second conductive member. The conductive structure at least penetrates the connecting structure layer and is electrically connected to the first conductive member and the second conductive member. The thermal interface material layer is disposed between the composite structure layer and the thermally conductive substrate, and the second structure layer is connected to the thermally conductive substrate through the thermal interface material layer.
    Type: Application
    Filed: April 6, 2021
    Publication date: March 24, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: Pei-Wei Wang, Shao-Chien Lee, Ra-Min Tain, Chi-Chun Po, Po-Hsiang Wang, Pei-Chang Huang, Chin-Min Hu
  • Patent number: 11280847
    Abstract: A circuit for parameter PSRR measurement includes a filter, a first regulator and a second regulator. The filter may be configured for receiving an AC input signal and a DC input signal, and for outputting a combined output signal according to the AC input signal and the DC input signal. The first regulator may be configured for receiving the combined output signal, and for outputting a first output signal having a first AC component signal and a first DC component signal. The second regulator may be configured for receiving the first output signal, and for outputting a second output signal having a second AC component signal and a second DC component signal. A parameter PSRR of the second regulator may be obtained according to the first AC component signal and the second AC component signal.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Amit Kundu, Jaw-Juinn Horng, Yi-Hsiang Wang
  • Publication number: 20220075219
    Abstract: The display device includes a first substrate; an active layer disposed on the first substrate; a first insulation layer disposed on the active layer; a first electrode layer disposed on the first insulation layer including a gate electrode line extending along a first direction and a protruding portion extending along a second direction; a second insulation layer disposed on the first electrode layer; and a second electrode layer disposed on the second insulation layer. The second electrode layer includes a date line extending along the second direction and a conductive layer. The conductive layer includes a first conductive portion and a second conductive portion, wherein the first conductive portion has a first maximum width A along the first direction, and the second conductive portion has a second maximum width B along the first direction. The first maximum width A is less than the second maximum width B.
    Type: Application
    Filed: November 12, 2021
    Publication date: March 10, 2022
    Inventors: Chung-Wen YEN, Yu-Tsung LIU, Chao-Hsiang WANG, Te-Yu LEE
  • Patent number: 11271811
    Abstract: The present invention provides a profile editing system, including: a plurality of devices; a plurality of device control modules, configured to respectively control the devices; and a profile control module, configured to record control settings that are preset by the device control modules for the devices as a profile, so that a user may enable the profile to make the devices work by using the control settings recorded in the profile, to form environmental conditions preset by the user.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: March 8, 2022
    Inventors: Chi-Hsiang Wang, Wan-Yu Hsien
  • Publication number: 20220068840
    Abstract: A semiconductor device package and manufacturing method thereof are provided. The semiconductor device package includes a first conductive structure, a second conductive structure, a connection element, a conductive member, an encapsulant and a binding layer. The first conductive structure includes a first circuit layer. The second conductive structure is disposed over the first conductive structure. The connection element is disposed on and electrically connected to the first circuit layer. The conductive member protrudes from the second conductive structure. The encapsulant is disposed between the first conductive structure and the second conductive structure. The binding layer is disposed between the second conductive structure and the encapsulant.
    Type: Application
    Filed: August 28, 2020
    Publication date: March 3, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-Jen CHENG, Po-Hsiang WANG, Fu-Yuan CHEN, Wei-Jen WANG
  • Patent number: 11255524
    Abstract: A light-emitting device including a substrate with a top surface and a bottom surface opposite to the top surface and a plurality of LED chips disposed on the top surface and configured to generate a top light visible above the top surface and a bottom light visible beneath the bottom surface, each LED chip comprising a plurality of light-emitting surfaces. The substrate has a thickness greater than 200 ?m and comprises aluminum oxide, sapphire, glass, plastic, or rubber. The plurality of LED chips has an incident light with a wavelength of 420-470 nm. The top light and the bottom light have a color temperature difference of not greater than 1500K.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: February 22, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Chi-Chih Pu, Chen-Hong Lee, Shih-Yu Yeh, Wei-Kang Cheng, Shyi-Ming Pan, Siang-Fu Hong, Chih-Shu Huang, Tzu-Hsiang Wang, Shih-Chieh Tang, Cheng-Kuang Yang
  • Publication number: 20220044748
    Abstract: A control system includes a plurality of driving circuits coupled in series, which includes a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a replica receiver. The first transmitter is coupled to the first receiver, and the replica receiver is coupled to an output terminal of the first transmitter. The second driving circuit, coupled to the first driving circuit, includes a second receiver and a second transmitter. The second receiver is coupled to the first transmitter, and the second transmitter is coupled to the second receiver.
    Type: Application
    Filed: June 30, 2021
    Publication date: February 10, 2022
    Applicant: NOVATEK Microelectronics Corp.
    Inventors: Che-Wei Yeh, Keko-Chun Liang, Yu-Hsiang Wang, Yong-Ren Fang, Yi-Chuan Liu, Yi-Yang Tsai, Po-Hsiang Fang
  • Publication number: 20220029091
    Abstract: A method for forming a memory device structure is provided. The method includes providing a substrate, a first dielectric layer, a conductive via, a magnetic tunnel junction cell, a first etch stop layer, and a first spacer layer. The substrate has a first region and a second region, the first dielectric layer is over the substrate, the conductive via passes through the first dielectric layer over the first region. The method includes removing the first etch stop layer, which is not covered by the first spacer layer. The method includes removing the first dielectric layer, which is not covered by the first etch stop layer.
    Type: Application
    Filed: July 21, 2020
    Publication date: January 27, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsing-Hsiang WANG, Han-Ting LIN, Yu-Feng YIN, Sin-Yi YANG, Chen-Jung WANG, Yin-Hao WU, Kun-Yi LI, Meng-Chieh WEN, Lin-Ting LIN, Jiann-Horng LIN, An-Shen CHANG, Huan-Just LIN
  • Publication number: 20220029622
    Abstract: A decoupling capacitance (decap) system which includes: a decap circuit electrically coupled between a first or second reference voltage rail and a first node; and a biasing circuit coupled between the first node and correspondingly the second or first reference voltage rail. Due to the series connection between the decap circuit and the biasing circuit, the voltage drop across the biasing circuit effectively reduces the voltage drop across the decap circuit so that the voltage drop across the decap circuit is less than a voltage drop across the decap system as whole.
    Type: Application
    Filed: February 4, 2021
    Publication date: January 27, 2022
    Inventors: Szu-Lin LIU, Yi-Hsiang WANG, Jaw-Juinn HORNG
  • Publication number: 20220013052
    Abstract: A source driver adapted to drive a display panel is provided. The source driver includes an output buffer and a slew rate adjustment circuit. An input terminal of the output buffer receives a driving voltage. An output terminal of the output buffer outputs an output signal adapted to drive the display panel. The slew rate adjustment circuit dynamically adjusts a slew rate of a rising edge of the output signal according to a first setting and dynamically adjusts a slew rate of a falling edge of the output signal according to a second setting independent of the first setting, such that the adjustment to the slew rate of the rising edge of the output signal is independent of the adjustment to the slew rate of the falling edge of the output signal.
    Type: Application
    Filed: December 10, 2020
    Publication date: January 13, 2022
    Applicant: Novatek Microelectronics Corp.
    Inventors: Ying-Hsiang Wang, Chia-Lun Chang
  • Publication number: 20220006608
    Abstract: A transmitter is configured to transmit a series of command signals and a series of data signals. The transmitter includes a serializer and a multiplexer. The serializer is configured to generate the series of data signals.
    Type: Application
    Filed: January 31, 2021
    Publication date: January 6, 2022
    Inventors: Yong-Ren Fang, Yu-Hsiang Wang, Che-Wei Yeh
  • Publication number: 20210399207
    Abstract: A magnetic tunnel junction (MTJ) memory cell comprising a connection via structure, a bottom electrode disposed on the connection via structure, a memory material stack disposed on the bottom electrode, and a conductive contact structure disposed on the memory material stack, in which a bottom surface of the conductive contact structure is in direct contact with a memory material layer of the memory material stack.
    Type: Application
    Filed: April 14, 2021
    Publication date: December 23, 2021
    Inventors: Hsing-Hsiang WANG, Yu-Feng YIN, Jiann-Horng LIN, Huan-Just LIN
  • Patent number: 11199565
    Abstract: An undervoltage detection circuit includes a voltage divider, a voltage-to-current (V-to-I) converter and a current comparator. The voltage divider divides a supply voltage to generate a divided voltage. The V-to-I converter converts the divided voltage into a first current based on a first V-to-I transfer function, and converts the divided voltage into a second current based on a second V-to-I transfer function different from the first V-to-I transfer function. The current comparator compares the first and second currents to generate a comparison signal that indicates whether the supply voltage is sufficiently large.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: December 14, 2021
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Ying-Hsiang Wang, Jung-Hsing Liao
  • Patent number: 11201110
    Abstract: A semiconductor device package includes a conductive layer, a first conductive pillar, a circuit layer and a second conductive pillar. The conductive layer has a first surface. The first conductive pillar is disposed on the first surface of the conductive layer. The circuit layer is disposed over the conductive layer. The circuit layer has a first surface facing the conductive layer. The second conductive pillar is disposed on the first surface of the circuit layer. The first conductive pillar is physically spaced apart from the second conductive pillar and electrically connected to the second conductive pillar.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: December 14, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Min Lung Huang, Hung-Jung Tu, Hsin Hsiang Wang
  • Patent number: 11199752
    Abstract: The display device includes a first substrate; an active layer disposed on the first substrate; a first insulation layer disposed on the active layer; a first electrode layer disposed on the first insulation layer including a gate electrode line extending along a first direction and a protruding portion extending along a second direction; a second insulation layer disposed on the first electrode layer; and a second electrode layer disposed on the second insulation layer. The second electrode layer includes a date line extending along the second direction and a conductive layer. The conductive layer includes a first conductive portion and a second conductive portion, wherein the first conductive portion has a first maximum width A along the first direction, and the second conductive portion has a second maximum width B along the first direction. The first maximum width A is less than the second maximum width B.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: December 14, 2021
    Assignee: INNOLUX CORPORATION
    Inventors: Chung-Wen Yen, Yu-Tsung Liu, Chao-Hsiang Wang, Te-Yu Lee