Patents by Inventor Hsuan Lin

Hsuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240076417
    Abstract: The present disclosure provides a method for manufacturing an auto-crosslinked hyaluronic acid gel, comprising conducting auto-crosslinking reaction of a colloid containing hyaluronic acid continuously at low temperature in an acidic environment, and treating the reaction product with steam at high temperature to obtain the auto-crosslinked hyaluronic acid gel with high viscosity.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 7, 2024
    Applicant: SCIVISION BIOTECH INC.
    Inventors: TAI-SHIEN HAN, TSUNG-WEI PAN, TOR-CHERN CHEN, CHUN-CHANG CHEN, PO-HSUAN LIN, LI-SU CHEN
  • Publication number: 20240071362
    Abstract: In example implementations, a computing device is provided. The computing device includes a system management bus, a controller communicatively coupled to the system management bus, a noise generating component communicatively coupled to the controller, a noise cancellation codec communicatively coupled to the system management bus, and a speaker communicatively coupled to the noise cancellation codec. The operating parameters of the noise generating component are provided to the controller. The noise cancellation codec is to receive the operating parameters of the noise generating component from the controller via the system management bus and to generate a noise cancellation signal based on the operating parameters. The speaker outputs the noise cancellation signal to cancel noise generated by the noise generating component.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Inventors: Chao-Wen Cheng, Tsung Yen Chen, Wen Shih Chen, Mo-Hsuan Lin, Juiching Chang
  • Publication number: 20240069618
    Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.
    Type: Application
    Filed: April 27, 2023
    Publication date: February 29, 2024
    Inventors: Wen Che CHUNG, Hui Chuan LO, Hao-Hsuan LIN, Chun TSAO, Jun-Fu CHEN, Ming-Hung YAO, Jia-Wei ZHANG, Kuan-Lun CHEN, Ting-Chao LIN, Cheng-Yen LIN, Chunyen LAI
  • Patent number: 11901229
    Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Yi Chen, Sheng-Hsuan Lin, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
  • Patent number: 11894674
    Abstract: A power detection circuit is provided. The protection circuit is coupled to a pad and includes a trigger circuit and a discharge circuit. The trigger circuit includes a first transistor of a first conductivity type and a second transistor, also of the first conductivity type, which are coupled in series between the pad and a ground terminal. The trigger circuit detects whether a transient even occurs on the pad. The discharge circuit is coupled between the bonding pad and the ground terminal and controlled by the trigger circuit. In response to the transient event occurring on the bonding pad, the trigger circuit generates a trigger voltage to trigger the discharge circuit to provide a discharge path between the pad and the ground terminal.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: February 6, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Jian-Hsing Lee, Yeh-Ning Jou, Chih-Hsuan Lin, Chang-Min Lin, Hwa-Chyi Chiou
  • Patent number: 11894430
    Abstract: A semiconductor structure, including a substrate, a first well, a second well, a first doped region, a second doped region, a first gate structure, a first insulating layer, and a first field plate structure. The first and second wells are disposed in the substrate. The first doped region is disposed in the first well. The second doped region is disposed in the second well. The first gate structure is disposed between the first and second doped regions. The first insulating layer covers a portion of the first well and a portion of the first gate structure. The first field plate structure is disposed on the first insulating layer, and it partially overlaps the first gate structure. Wherein the first field plate structure is segmented into a first partial field plate and a second partial field plate separated from each other along a first direction.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: February 6, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang Huang, Kai-Chieh Hsu, Chun-Chih Chen, Chih-Hsuan Lin
  • Publication number: 20240038658
    Abstract: A semiconductor device includes a source region and a drain region, a first source contact, a first drain contact, a first drain via and a first source via. The source region and the drain region are located over a substrate. The first source contact is disposed on the source region, and the first drain contact is disposed on the drain region. The first drain via is connected to the first drain contact, wherein the first drain via includes a barrier-less body portion. The first source via is connected to the first source contact, wherein the first source via includes a body portion and a barrier layer surrounding the body portion, and a size of the first source via is greater than a size of the first drain via.
    Type: Application
    Filed: July 26, 2022
    Publication date: February 1, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chiang Tsai, Pei-Hsuan Lin, Jeng-Ya Yeh, Mu-Chi Chiang
  • Publication number: 20240028813
    Abstract: A semiconductor layout including a semiconductor layer and a dummy layer is provided. The semiconductor layer includes a layout pattern. The dummy layer includes a dummy pattern. A check circuit calculates the layout pattern and the dummy pattern to generate a calculated value. The check circuit compares the calculated value to the predetermined value to determine whether the layout pattern has been modified.
    Type: Application
    Filed: July 25, 2022
    Publication date: January 25, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Yeh-Ning JOU, Chih-Hsuan LIN, Shu-Pin HSU, Hwa-Chyi CHIOU, Chang-Min LIN, Tsong-Shyan CHEN
  • Publication number: 20240030821
    Abstract: A novel power supply apparatus (10) includes a microcontroller (102) and a plurality of voltage converters (104). If the voltage converters (104) are in a boost mode and a plurality of duty cycles of the voltage converters (104) calculated by the microcontroller (102) are less than 0.5, the microcontroller (102) is configured to limit at least one of the duty cycles of the voltage converters (104) to 0.5. If the voltage converters (104) are in a buck mode and the duty cycles of the voltage converters (104) calculated by the microcontroller (102) are greater than 0.5, the microcontroller (102) is configured to limit at least one of the duty cycles of the voltage converters (104) to 0.5.
    Type: Application
    Filed: July 25, 2022
    Publication date: January 25, 2024
    Inventors: Lien-Hsing CHEN, Ta-Wen CHANG, Hsiao-Hua CHI, Ching-Ming LAI, Wei-Hsuan LIN
  • Publication number: 20240022006
    Abstract: A multi-beam antenna module includes a radio frequency circuit board, a plurality of reflecting plates and a plurality of area coverage feed antenna groups. Each of the area coverage feed antenna groups includes a feed antenna. The reflecting plates have different arrangement directions, and each of the reflecting plates is arranged relative to the feed antenna of each of the area coverage feed antenna groups, thereby changing a radiation pattern of the feed antenna of each of the area coverage feed antenna groups to deflect a main radiation direction of the feed antenna of each of the area coverage feed antenna groups.
    Type: Application
    Filed: July 14, 2022
    Publication date: January 18, 2024
    Inventor: Hung-Hsuan LIN
  • Patent number: 11876945
    Abstract: A method for acquiring shadow-free images of a document for scanning or other purposes is applied in a device. The method includes training a shadow prediction model based on sample documents of a sample library and inputting a background color and a shadow mask of each of the sample documents extracted by the shadow prediction model into a predetermined shadow removing network for training, to obtain a shadow removing model. The method further includes obtaining a background color and a shadow mask of the document through the shadow prediction model and removing the shadows of the document based on the shadow removing model. The device utilizing the method is also disclosed.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: January 16, 2024
    Assignee: Mobile Drive Netherlands B.V.
    Inventors: Yun-Hsuan Lin, Yung-Yu Chuang, Nai-Sheng Syu, Tzu-Kuei Huang, Ting-Hao Chung, Yu-Ching Wang, Chun-Hsiang Huang
  • Patent number: 11875849
    Abstract: An analog content-address memory (analog CAM) having approximation matching and an operation method thereof are provided. The analog CAM includes an inputting circuit, at least one analog CAM cell and an outputting circuit. The inputting circuit is configured to provide an inputting data. The analog CAM cell is connected to the inputting circuit and receives the inputting data. The analog CAM cell has a mild swing match curve whose highest point corresponds to a stored data. A segment from the highest point of the mild swing match curve to a lowest point of the mild swing match curve corresponds to at least three data values. The outputting circuit is connected to the analog CAM cell and receives a match signal from the analog CAM cell. The outputting circuit outputs a match approximation level according to the match signal.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: January 16, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Hsuan Lin, Po-Hao Tseng, Feng-Min Lee
  • Patent number: 11874703
    Abstract: A mobile dock is provided. The mobile dock is configured to electrically coupled to a mobile device having a first identifier and an application, and includes a control unit, a memory unit and an I/O module. The memory unit is electrically coupled to the control unit and stores at least a second identifier and at least a configuration file. The I/O module includes an I/O unit, a mobile port and an I/O port, and the mobile port is configured to electrically coupled to the mobile device. When the mobile device is electrically coupled to the mobile dock, the control unit receives the first identifier and triggers the configuration file corresponding to the first identifier, and transmits the second identifier corresponding to the first identifier to the mobile device. The mobile device receives the second identifier and triggers the application.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: January 16, 2024
    Assignee: DEXIN CORPORATION
    Inventors: Ho Lung Lu, Hsiu Hsuan Lin, Yuan Jung Chang
  • Patent number: 11866838
    Abstract: A method for creating colorful patterns on a metal surface by using colorless ink is revealed. First carry out a first anodizing process on a metal substrate to form a first anodic oxide layer on a surface of the metal substrate. Then coat a layer of colorless ink on the first anodic oxide layer on the surface of the metal substrate to form a colorless ink pattern mask. Later perform a second anodizing process to form a second anodic oxide layer on a part of the metal substrate without being covered with the colorless ink pattern mask. Next remove the colorless ink pattern mask and coat a metal film over the first anodic oxide layer and the second anodic oxide layer to get a colorful pattern on the metal substrate.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: January 9, 2024
    Assignee: National Cheng Kung University
    Inventors: Chen-Kuei Chung, Chin-Jou Kuo, Wei-Hsuan Lin
  • Patent number: 11871539
    Abstract: An electronic apparatus with a cooling system includes a chassis having a mounting slot, and a removable device. The removable device includes a housing detachably disposed in the mounting slot; a first pump disposed in the housing, and detachably affixed to a bottom of the housing; a second pump detachably affixed to the bottom of the housing, and connected to the first pump; and a tank disposed on the first pump and configured to store cooling liquid. when the first pump or the second pump is operating, the cooling liquid in the tank flows into the first pump, and the cooling liquid in the first pump flows into the second pump.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: January 9, 2024
    Assignee: Nanning FuLian FuGui Precision Industrial Co., Ltd.
    Inventor: Chih-Hsuan Lin
  • Patent number: 11871588
    Abstract: A memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: January 9, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Feng-Min Lee, Erh-Kun Lai, Dai-Ying Lee, Yu-Hsuan Lin, Po-Hao Tseng, Ming-Hsiu Lee
  • Publication number: 20240000983
    Abstract: A microbial inhibition device for inhibiting microorganisms on a predetermined object includes: a covering member covering the predetermined object, and having an attachment surface for attaching to the predetermined object, and an exposed surface opposite to the attachment surface, wherein the covering member includes at least a conductive medium layer, and the conductive medium layer constitutes a predetermined area of the exposed surface; a control module configured to issue a control command reflecting a predetermined conduction mode; and a power supply module electrically connected to the conductive medium layer, and configured to receive the control command so as to power the conductive medium layer according to the predetermined conduction mode based on the control command. The conductive medium layer is conducted with current according to the predetermined conduction mode through the power supply module. Accordingly predetermined microorganisms on the predetermined area are inhibited or killed.
    Type: Application
    Filed: January 31, 2023
    Publication date: January 4, 2024
    Inventors: HSIN-YI TSAI, YU-HSUAN LIN, CHUN-HAN CHOU, KUO-CHENG HUANG, CHING-CHING YANG
  • Publication number: 20240000978
    Abstract: A method of tracking immune cells to detect immune response. The method including steps of identifying a patient having a disease associated with an organ; administering biocompatible magnetic nanoparticles into the blood stream of the patient; and obtaining a magnetic resonance image of the organ. The presence of hyperintense or hypointense spots in the magnetic resonance image indicates immune response in the patient.
    Type: Application
    Filed: August 7, 2023
    Publication date: January 4, 2024
    Inventors: Chih-Lung Chen, Wen-Yuan Hsieh, Chen-Hsuan Lin, Shian-Jy Wang
  • Publication number: 20240003692
    Abstract: A method includes: receiving an auxiliary routing request from a manufacturing execution system (MES) apparatus of a first site by an inter-site backup management apparatus; selecting an auxiliary route to a second site based on the auxiliary routing request and a statistical model by the inter-site backup management apparatus; including the auxiliary route in a route associated with a wafer lot by the MES apparatus; and performing a semiconductor processing operation on a wafer of the wafer lot according to the route.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Inventors: Mei-Hsuan Lin, Rong Syuan Fan, Jen-Yuan Chang
  • Patent number: 11854874
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou