Patents by Inventor Hsuan Lin

Hsuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240257460
    Abstract: Apparatuses, systems, and techniques to generate pixels based on other pixels. In at least one embodiment, one or more neural networks are used to generate one or more pixels based, at least in part, on sets of pixels surrounding the one or more pixels.
    Type: Application
    Filed: November 18, 2022
    Publication date: August 1, 2024
    Inventors: Chen-Hsuan Lin, Zhaoshuo Li, Thomas Müller-Höhne, Alex John Bauld Evans, Ming-Yu Liu, Alexander Georg Keller
  • Publication number: 20240257873
    Abstract: A hybrid in-memory search (IMS) content addressable memory (CAM) cell includes: a first IMS CAM cell; and a second IMS CAM cell, coupled to the first IMS CAM cell. The first IMS CAM cell and the second IMS CAM cell are of different types. When the hybrid IMS CAM cell stores a storage data, the first IMS CAM cell stores a first part of the storage data and the second IMS CAM cell stores the storage data or a second part of the storage data.
    Type: Application
    Filed: February 1, 2023
    Publication date: August 1, 2024
    Inventors: Po-Hao TSENG, Yu-Hsuan LIN, Tian-Cih BO, Feng-Min LEE, Yu-Yu LIN
  • Patent number: 12046609
    Abstract: A solid-state image sensor is provided. The solid-state image sensor includes photoelectric conversion elements and a color filter layer disposed above the photoelectric conversion elements. The photoelectric conversion elements and the color filter layer form normal pixels and auto-focus pixels, the color filter layer that correspond to the normal pixels are divided into first color filter segments and second color filter segments, the first color filter segments are disposed on at least one side that is closer to an incident light, and the width of the first color filter segments is greater than the width of the second color filter segments.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: July 23, 2024
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Ching-Hua Li, Cheng-Hsuan Lin, Zong-Ru Tu, Yu-Chi Chang, Han-Lin Wu
  • Publication number: 20240242767
    Abstract: A storage device for generating an identity code, includes a first storage circuit, a second storage circuit and a reading circuit. The first storage circuit stores several first data having several bits. The second storage circuit stores several second data having several bits. The reading circuit reads the second data from the second storage circuit to form a first sequence, and simultaneously reads the first data from the first storage circuit to form a second sequence. The reading circuit includes a processing circuit which simultaneously receives the first sequence and the second sequence, selects a first portion of the second sequence to form a target sequence according to the first sequence, and outputs the target sequence to serve as an identity code. Logical values of the bits of the first data and the second data are randomly distributed or pre-defined by a user.
    Type: Application
    Filed: April 1, 2024
    Publication date: July 18, 2024
    Inventors: Yu-Hsuan LIN, Dai-Ying LEE, Ming-Hsiu LEE
  • Publication number: 20240236875
    Abstract: A method for adjusting time-averaged (TA) parameters of a transmitting (TX) power of a radio module includes: obtaining at least one message of the at least one other radio module or at least one message of the radio module; determining a scenario of the TX power of the radio module according to the at least one message of the at least one other radio module or the at least one message of the radio module; determining whether the scenario is different from a predetermined scenario of the TX power of the radio module; and in response to the scenario being different from the predetermined scenario, adjusting the TA parameters according to the scenario.
    Type: Application
    Filed: October 2, 2023
    Publication date: July 11, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yi-Ying Huang, Yi-Hsuan Lin, Han-Chun Chang
  • Publication number: 20240222965
    Abstract: A driving circuit includes a detection circuit, a control circuit, and a power device. The detection circuit is coupled between first and second power terminals. The detection circuit generates a detection voltage at a detection node based on a first voltage of the first power terminal and a second voltage of the second power terminal. The control circuit includes a transistor device with a back-to-back connection structure that is coupled between a bonding pad and a first node and controlled by the detection voltage to generate a driving voltage at the first node for controlling the power device. In response to an electrostatic discharge event occurring on the bonding pad, the transistor device is turned on according to the detection voltage, and the power device is triggered by the driving voltage to provide a discharge path between the bonding pad and the second power terminal.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang HUANG, Ching-Ho LI, Chun-Chih CHEN, Kai-Chieh HSU, Chien-Wei WANG, Chih-Hsuan LIN, Hwa-Chyi CHIOU, Gong-Kai LIN, Li-Fan CHEN
  • Patent number: 12027548
    Abstract: An image sensor includes: a group of autofocus sensor units; neighboring sensor units adjacent to and surrounding the group of autofocus sensor units, wherein each of the neighboring sensor units has a first side close to the group of autofocus sensor units, and a second side away from the group of autofocus sensor units. The image sensor further includes: a first light shielding structure disposed between the group of autofocus sensor units and the neighboring sensor units; a first extra light shielding structure laterally extending from the first light shielding structure and disposed on at least one of the first side and the second side of one or more of the neighboring sensor units.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: July 2, 2024
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Cheng-Hsuan Lin, Yu-Chi Chang
  • Patent number: 12025338
    Abstract: In some examples, an electronic device includes an audio output device, an airflow generator to generate an airflow, and a system controller to control an operational speed of the airflow generator. The electronic device further includes an audio controller to generate a noise cancellation audio output based on an indicator of the operational speed of the airflow generator provided from the system controller to the audio controller, and send the noise cancellation audio output to the audio output device to mitigate noise produced by the airflow generator.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: July 2, 2024
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chao-Wen Cheng, Tsung-Yen Chen, Chien Fa Huang, Wen Shih Chen, Mo-Hsuan Lin
  • Publication number: 20240213241
    Abstract: An ESD protection device includes a substrate, an epitaxial layer, first to third well regions, and first to sixth doped regions. The first to third well regions are disposed in the epitaxial layer. The third well region is disposed between the first and second well regions. The first and second doped regions are disposed on the first well region and coupled to a pad. The third and fourth doped regions are disposed on the second well region and coupled to a ground terminal. The fifth doped region is disposed on the third well region, and the sixth doped region is disposed in the fifth doped region. The third, fifth, and sixth doped regions have the same conductive type. In response to an electrostatic discharge event occurring on the pad, a discharge path is formed between the pad and the ground terminal.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Yeh-Ning JOU, Jian-Hsing LEE, Chieh-Yao CHUANG, Hsien-Feng LIAO, Ting-Yu CHANG, Chih-Hsuan LIN, Wen-Hsin LIN, Hwa-Chyi CHIOU
  • Publication number: 20240213699
    Abstract: A conductive wire set includes a plurality of leads, a plurality of transfer terminals, and a conductive terminal. The plurality of leads are arranged with each other, and each of the leads extends along a first direction. Each of the leads has an outlet end. The plurality of transfer terminals each corresponds to one of the plurality of leads; each of the plurality of transfer terminals has a lead connection end and a plug end, and the lead connection end is connected to the outlet end of the corresponding lead. The conductive terminal includes a slot structure and a pin end. The slot structure has at least one slot for inserting the plug ends, and the pin end is opposite to the slot structure. The plug ends are inserted into at least one slot alongside and aligned with each other in a second direction other than the first direction.
    Type: Application
    Filed: April 26, 2023
    Publication date: June 27, 2024
    Applicant: ELKA INTERNATIONAL LTD.
    Inventors: Yuan-Hsi TING, Kai-Hsuan LIN, Ming-Chin HUANG
  • Patent number: 12021304
    Abstract: A multi-beam antenna module includes a radio frequency circuit board, a plurality of reflecting plates and a plurality of area coverage feed antenna groups. Each of the area coverage feed antenna groups includes a feed antenna. The reflecting plates have different arrangement directions, and each of the reflecting plates is arranged relative to the feed antenna of each of the area coverage feed antenna groups, thereby changing a radiation pattern of the feed antenna of each of the area coverage feed antenna groups to deflect a main radiation direction of the feed antenna of each of the area coverage feed antenna groups.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: June 25, 2024
    Assignee: WANSHIH ELECTRONIC CO., LTD.
    Inventor: Hung-Hsuan Lin
  • Publication number: 20240203885
    Abstract: A method of manufacturing a semiconductor device includes forming a first dielectric layer over a substrate, forming a metal layer in the first dielectric layer, forming an etch stop layer on a surface of the first dielectric layer and the metal layer, removing portions of the metal layer and the etch stop layer to form a recess in the metal layer, and forming a tungsten plug in the recess. The recess is spaced apart from a bottom surface of the etch stop layer.
    Type: Application
    Filed: February 28, 2024
    Publication date: June 20, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan LIN, Hsi Chung CHEN, Ji-Ling WU, Chih-Teng LIAO
  • Patent number: 12015350
    Abstract: A novel power supply apparatus (10) includes a microcontroller (102) and a plurality of voltage converters (104). If the voltage converters (104) are in a boost mode and a plurality of duty cycles of the voltage converters (104) calculated by the microcontroller (102) are less than 0.5, the microcontroller (102) is configured to limit at least one of the duty cycles of the voltage converters (104) to 0.5. If the voltage converters (104) are in a buck mode and the duty cycles of the voltage converters (104) calculated by the microcontroller (102) are greater than 0.5, the microcontroller (102) is configured to limit at least one of the duty cycles of the voltage converters (104) to 0.5.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: June 18, 2024
    Assignee: P-DUKE TECHNOLOGY CO., LTD.
    Inventors: Lien-Hsing Chen, Ta-Wen Chang, Hsiao-Hua Chi, Ching-Ming Lai, Wei-Hsuan Lin
  • Publication number: 20240194668
    Abstract: An electrostatic discharge protection structure includes a semiconductor substrate and a first n-type well region, a p-type well region, a first p-type doped region, a second p-type doped region, and an isolation structure disposed in the semiconductor substrate. The p-type well region is located adjacent to the first n-type well region. The first p-type doped region and the second p-type doped region are located above the first n-type well region and the p-type well region, respectively. A first portion of the isolation structure is located between the first p-type doped region and the second p-type doped region in a horizontal direction. An edge of the first n-type well region is located under the first portion. A distance between the first p-type doped region and the edge of the first n-type well region in the horizontal direction is less than a length of the first portion in the horizontal direction.
    Type: Application
    Filed: February 3, 2023
    Publication date: June 13, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsuan Lin, Hou-Jen Chiu, Mei-Ling Chao, Tien-Hao Tang, Kuan-Cheng Su
  • Publication number: 20240184464
    Abstract: A method for operating a memory device is provided. The method includes following steps. First, a priority of a refresh operation and a priority of an inference operation for at least a portion of a memory array of the memory device are determined. The refresh operation and the inference operation are performed according to a determination result of the priority of the refresh operation and the priority of the inference operation. If the priority of the refresh operation is lower than the priority of inference operation, perform the inference operation in the at least a portion, and perform the refresh operation after performing the inference operation. If the priority of the refresh operation is higher than the priority of inference operation, perform the refresh operation in the at least a portion, and perform the inference operation after performing the refresh operation.
    Type: Application
    Filed: April 19, 2023
    Publication date: June 6, 2024
    Inventors: Yu-Hsuan LIN, Hsiang-Lan LUNG, Cheng-Lin SUNG
  • Publication number: 20240174894
    Abstract: A composite film includes a first thermoplastic elastomer film layer and a second thermoplastic elastomer film layer, wherein the first thermoplastic elastomer film layer includes a first styrenic block copolymer. The second thermoplastic elastomer film layer is disposed on the first thermoplastic elastomer film layer, wherein the second thermoplastic elastomer film layer includes a second styrenic block copolymer, diffusion particles dispersed in the second thermoplastic elastomer film layer, and a surface microstructure disposed on the surface of the second thermoplastic elastomer film layer.
    Type: Application
    Filed: April 27, 2023
    Publication date: May 30, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Cheng-Hsuan Lin, Yu-Ling Hsu, Chun-Chen Chiang, Yi-Ping Chen
  • Publication number: 20240170953
    Abstract: An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes first, second, and third transistors and a discharge circuit. The first transistor has a first gate, a first drain coupled to the bonding pad, and a first source coupled to a first node. The second transistor has a second gate coupled to a power terminal, a second drain coupled to the first gate, and a second source coupled to a ground. The third transistor has a third gate coupled to the power terminal, a third drain coupled to the first node, and a third source coupled to the ground. The discharge circuit is controlled by a driving voltage at the first node. In response to an electrostatic discharge event occurring on the bonding pad, the discharge circuit provides a discharge path between the bonding pad and the ground according to the driving voltage.
    Type: Application
    Filed: November 17, 2022
    Publication date: May 23, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Hsuan LIN, Shao-Chang HUANG, Wen-Hsin LIN, Yeh-Ning JOU, Hwa-Chyi CHIOU, Chun-Chih CHEN
  • Patent number: 11990524
    Abstract: A method includes forming a dummy gate structure across a fin, in which the dummy gate structure has a dummy gate dielectric layer and a dummy gate electrode, forming gate spacers on sidewalls of the dummy gate structure, forming source/drain epitaxial structures on sides of the dummy gate structure, performing a first etch process to the dummy gate electrode such that a recessed dummy gate electrode remains over the fin, performing a second etch process to the gate spacers such that recessed gate spacers remain over the sidewalls of the dummy gate structure, removing the recessed dummy gate electrode and the dummy gate dielectric layer after the second etch process to form a recess between the recessed gate spacers, forming a gate structure overfilling the recess, and performing a third etch process to the gate structure such that a recessed gate structure remains between the recessed gate spacers.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Chien Lin, Hsi Chung Chen, Cheng-Hung Tsai, Chih-Hsuan Lin
  • Patent number: RE49993
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: June 4, 2024
    Assignee: Logitech Europe S.A.
    Inventors: Marcel Twohig, Yi Hsuan Lin, Anish Shakthi Ovia Selvan, Jean-Christophe Hemes, Jasper Phua, Blaithin Crampton
  • Patent number: D1033422
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: July 2, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Han-Sheng Siao, Yi-Hsuan Lin, Yen-Hua Hsiao, Yun-Tung Pai, Yi-Hung Chen, Chuan-Fong Lee