Patents by Inventor Hsuan Lin

Hsuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12021304
    Abstract: A multi-beam antenna module includes a radio frequency circuit board, a plurality of reflecting plates and a plurality of area coverage feed antenna groups. Each of the area coverage feed antenna groups includes a feed antenna. The reflecting plates have different arrangement directions, and each of the reflecting plates is arranged relative to the feed antenna of each of the area coverage feed antenna groups, thereby changing a radiation pattern of the feed antenna of each of the area coverage feed antenna groups to deflect a main radiation direction of the feed antenna of each of the area coverage feed antenna groups.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: June 25, 2024
    Assignee: WANSHIH ELECTRONIC CO., LTD.
    Inventor: Hung-Hsuan Lin
  • Publication number: 20240203885
    Abstract: A method of manufacturing a semiconductor device includes forming a first dielectric layer over a substrate, forming a metal layer in the first dielectric layer, forming an etch stop layer on a surface of the first dielectric layer and the metal layer, removing portions of the metal layer and the etch stop layer to form a recess in the metal layer, and forming a tungsten plug in the recess. The recess is spaced apart from a bottom surface of the etch stop layer.
    Type: Application
    Filed: February 28, 2024
    Publication date: June 20, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan LIN, Hsi Chung CHEN, Ji-Ling WU, Chih-Teng LIAO
  • Patent number: 12015350
    Abstract: A novel power supply apparatus (10) includes a microcontroller (102) and a plurality of voltage converters (104). If the voltage converters (104) are in a boost mode and a plurality of duty cycles of the voltage converters (104) calculated by the microcontroller (102) are less than 0.5, the microcontroller (102) is configured to limit at least one of the duty cycles of the voltage converters (104) to 0.5. If the voltage converters (104) are in a buck mode and the duty cycles of the voltage converters (104) calculated by the microcontroller (102) are greater than 0.5, the microcontroller (102) is configured to limit at least one of the duty cycles of the voltage converters (104) to 0.5.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: June 18, 2024
    Assignee: P-DUKE TECHNOLOGY CO., LTD.
    Inventors: Lien-Hsing Chen, Ta-Wen Chang, Hsiao-Hua Chi, Ching-Ming Lai, Wei-Hsuan Lin
  • Publication number: 20240194668
    Abstract: An electrostatic discharge protection structure includes a semiconductor substrate and a first n-type well region, a p-type well region, a first p-type doped region, a second p-type doped region, and an isolation structure disposed in the semiconductor substrate. The p-type well region is located adjacent to the first n-type well region. The first p-type doped region and the second p-type doped region are located above the first n-type well region and the p-type well region, respectively. A first portion of the isolation structure is located between the first p-type doped region and the second p-type doped region in a horizontal direction. An edge of the first n-type well region is located under the first portion. A distance between the first p-type doped region and the edge of the first n-type well region in the horizontal direction is less than a length of the first portion in the horizontal direction.
    Type: Application
    Filed: February 3, 2023
    Publication date: June 13, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsuan Lin, Hou-Jen Chiu, Mei-Ling Chao, Tien-Hao Tang, Kuan-Cheng Su
  • Publication number: 20240184464
    Abstract: A method for operating a memory device is provided. The method includes following steps. First, a priority of a refresh operation and a priority of an inference operation for at least a portion of a memory array of the memory device are determined. The refresh operation and the inference operation are performed according to a determination result of the priority of the refresh operation and the priority of the inference operation. If the priority of the refresh operation is lower than the priority of inference operation, perform the inference operation in the at least a portion, and perform the refresh operation after performing the inference operation. If the priority of the refresh operation is higher than the priority of inference operation, perform the refresh operation in the at least a portion, and perform the inference operation after performing the refresh operation.
    Type: Application
    Filed: April 19, 2023
    Publication date: June 6, 2024
    Inventors: Yu-Hsuan LIN, Hsiang-Lan LUNG, Cheng-Lin SUNG
  • Publication number: 20240174894
    Abstract: A composite film includes a first thermoplastic elastomer film layer and a second thermoplastic elastomer film layer, wherein the first thermoplastic elastomer film layer includes a first styrenic block copolymer. The second thermoplastic elastomer film layer is disposed on the first thermoplastic elastomer film layer, wherein the second thermoplastic elastomer film layer includes a second styrenic block copolymer, diffusion particles dispersed in the second thermoplastic elastomer film layer, and a surface microstructure disposed on the surface of the second thermoplastic elastomer film layer.
    Type: Application
    Filed: April 27, 2023
    Publication date: May 30, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Cheng-Hsuan Lin, Yu-Ling Hsu, Chun-Chen Chiang, Yi-Ping Chen
  • Publication number: 20240170953
    Abstract: An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes first, second, and third transistors and a discharge circuit. The first transistor has a first gate, a first drain coupled to the bonding pad, and a first source coupled to a first node. The second transistor has a second gate coupled to a power terminal, a second drain coupled to the first gate, and a second source coupled to a ground. The third transistor has a third gate coupled to the power terminal, a third drain coupled to the first node, and a third source coupled to the ground. The discharge circuit is controlled by a driving voltage at the first node. In response to an electrostatic discharge event occurring on the bonding pad, the discharge circuit provides a discharge path between the bonding pad and the ground according to the driving voltage.
    Type: Application
    Filed: November 17, 2022
    Publication date: May 23, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Hsuan LIN, Shao-Chang HUANG, Wen-Hsin LIN, Yeh-Ning JOU, Hwa-Chyi CHIOU, Chun-Chih CHEN
  • Patent number: 11990524
    Abstract: A method includes forming a dummy gate structure across a fin, in which the dummy gate structure has a dummy gate dielectric layer and a dummy gate electrode, forming gate spacers on sidewalls of the dummy gate structure, forming source/drain epitaxial structures on sides of the dummy gate structure, performing a first etch process to the dummy gate electrode such that a recessed dummy gate electrode remains over the fin, performing a second etch process to the gate spacers such that recessed gate spacers remain over the sidewalls of the dummy gate structure, removing the recessed dummy gate electrode and the dummy gate dielectric layer after the second etch process to form a recess between the recessed gate spacers, forming a gate structure overfilling the recess, and performing a third etch process to the gate structure such that a recessed gate structure remains between the recessed gate spacers.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Chien Lin, Hsi Chung Chen, Cheng-Hung Tsai, Chih-Hsuan Lin
  • Publication number: 20240161403
    Abstract: Text-to-image generation generally refers to the process of generating an image from one or more text prompts input by a user. While artificial intelligence has been a valuable tool for text-to-image generation, current artificial intelligence-based solutions are more limited as it relates to text-to-3D content creation. For example, these solutions are oftentimes category-dependent, or synthesize 3D content at a low resolution. The present disclosure provides a process and architecture for high-resolution text-to-3D content creation.
    Type: Application
    Filed: August 9, 2023
    Publication date: May 16, 2024
    Inventors: Chen-Hsuan Lin, Tsung-Yi Lin, Ming-Yu Liu, Sanja Fidler, Karsten Kreis, Luming Tang, Xiaohui Zeng, Jun Gao, Xun Huang, Towaki Takikawa
  • Publication number: 20240162359
    Abstract: A backsheet of a solar cell module including a substrate, a first protection layer, and a second protection layer is provided. The substrate includes a first surface and a second surface opposite to each other. The first protection layer is disposed on the first surface of the substrate. The second protection layer is disposed on the second surface of the substrate, wherein the first protection layer and the second protection layer include a silicone layer. At least one of the first protection layer and the second protection layer includes diffusion particles, wherein the diffusion particles include zinc oxide, titanium dioxide modified with silicon dioxide, or a combination thereof. A thickness of the first protection layer and a thickness of the second protection layer are respectively 10 ?m to 30 ?m. A solar cell module including the backsheet is also provided.
    Type: Application
    Filed: January 9, 2023
    Publication date: May 16, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Chih-Kang Peng, Cheng-Hsuan Lin, Yu-Ling Hsu, Chun-Chen Chiang
  • Patent number: 11980694
    Abstract: A sterilization apparatus for a portable electronic device including a cabinet and a carrier is provided. The carrier includes a base slidably disposed on the cabinet, multiple first positioning elements and multiple second positioning elements disposed in parallel on the base, multiple sterilization light sources corresponding to the second positioning elements and multiple pressure sensors disposed in parallel in the base. The base is configured to carry at least one portable electronic device. One second positioning element is disposed between any two adjacent first positioning elements, and any first positioning element and any second positioning element adjacent to each other are separated by a positioning space. The pressure sensors are respectively located in the positioning spaces. One sterilization light source is disposed between any two adjacent pressure sensors, and the pressure sensors are configured to sense a pressure from the portable electronic device.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: May 14, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yi-Hung Chen, Chih-Wen Chiang, Yun-Tung Pai, Yen-Hua Hsiao, Yao-Kuang Su, Yi-Hsuan Lin, Han-Sheng Siao
  • Patent number: 11984166
    Abstract: A storage device for generating an identity code and an identity code generating method are disclosed. The storage device includes a first storage circuit, a second storage circuit and a reading circuit. The first storage circuit stores a plurality of first data and the first data have a plurality of bits. The second storage circuit stores a plurality of second data and the second data have a plurality of bits. The reading circuit reads the second data from the second storage circuit to form a first sequence, selects a first portion of the first data according to the first sequence, reads the first portion of the first data from the first storage circuit to form a target sequence and outputs the target sequence to serve as an identity code.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: May 14, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Hsuan Lin, Dai-Ying Lee, Ming-Hsiu Lee
  • Publication number: 20240136227
    Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Ching-Yi Chen, Sheng-Hsuan Lin, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
  • Publication number: 20240137875
    Abstract: A method for adjusting time-averaged (TA) parameters of a transmitting (TX) power of a radio module includes: obtaining at least one message of the at least one other radio module or at least one message of the radio module; determining a scenario of the TX power of the radio module according to the at least one message of the at least one other radio module or the at least one message of the radio module; determining whether the scenario is different from a predetermined scenario of the TX power of the radio module; and in response to the scenario being different from the predetermined scenario, adjusting the TA parameters according to the scenario.
    Type: Application
    Filed: October 1, 2023
    Publication date: April 25, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yi-Ying Huang, Yi-Hsuan Lin, Han-Chun Chang
  • Publication number: 20240118329
    Abstract: An apparatus is provided. The apparatus includes a laser generation device configured to emit a laser signal to a semiconductor fabrication component. The apparatus includes a reflection detection device configured to receive a reflection signal comprising light, of the laser signal, reflected by a surface of the semiconductor fabrication component. The reflection detection device includes an optical filter. The optical filter is configured to block light, of the reflection signal, that has a wavelength outside a defined range of wavelengths. The optical filter is configured to provide filtered light, from the reflection signal, that has a wavelength within the defined range of wavelengths. The reflection detection device includes a light sensor configured to generate an electrical signal based upon the filtered light. The apparatus includes a computer configured to determine, based upon the electrical signal, measures of electrostatic field strength at the surface of the semiconductor fabrication component.
    Type: Application
    Filed: May 11, 2023
    Publication date: April 11, 2024
    Inventors: Ming Da YANG, Yi-Chen LI, Chun-Hsuan LIN
  • Patent number: 11955430
    Abstract: A method of manufacturing a semiconductor device includes forming a first dielectric layer over a substrate, forming a metal layer in the first dielectric layer, forming an etch stop layer on a surface of the first dielectric layer and the metal layer, removing portions of the metal layer and the etch stop layer to form a recess in the metal layer, and forming a tungsten plug in the recess. The recess is spaced apart from a bottom surface of the etch stop layer.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hsuan Lin, Hsi Chung Chen, Ji-Ling Wu, Chih-Teng Liao
  • Patent number: 11952676
    Abstract: A silicon carbide crystal includes a seed layer, a bulk layer and a stress buffering structure formed between the seed layer and the bulk layer. The seed layer, the bulk layer and the stress buffering structure are each formed with a dopant that cycles between high and low dopant concentration. The stress buffering structure includes a plurality of stacked buffer layers and a transition layer over the buffer layers. The buffer layer closest to the seed layer has the same variation trend of the dopant concentration as the buffer layer closest to the transition layer, and the dopant concentration of the transition layer is equal to the dopant concentration of the seed layer.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: April 9, 2024
    Assignee: GLOBALWAFERS CO., LTD.
    Inventors: Ching-Shan Lin, Jian-Hsin Lu, Chien-Cheng Liou, Man-Hsuan Lin
  • Patent number: 11955865
    Abstract: A three-axis voice coil motor including a base, a spherical bearing, a magnetic component, an X-coil group, a Y-coil group, and at least one Z-coil group is provided. The base has a supporting pole. The spherical bearing is rotatably sleeved around the supporting pole. The magnetic component is securely sleeved around the spherical bearing and the magnetic component rotates along with the spherical bearing. The X-coil group is disposed around the magnetic component along an X-axial direction passing through the spherical bearing, and the X-coil group has first gaps. The Y-coil group is disposed around the magnetic component along a Y-axial direction passing through the spherical bearing, and the Y-coil group has second gaps. The Z-coil group is disposed around the magnetic component along a Z-axial direction passing through the spherical bearing.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: April 9, 2024
    Assignee: National Cheng-Kung University
    Inventors: Chien-Sheng Liu, Yi-Hsuan Lin, Chiu-Nung Yeh
  • Patent number: D1025064
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: April 30, 2024
    Assignee: Logitech Europe S.A.
    Inventors: Yi-Hsuan Lin, Blaithin Crampton, Marcel Twohig, Anish Shakthi Ovia Selvan, Anatoliy Polyanker, Jingyan Ma, Ming Feng Hsieh, Olivia Hildebrand
  • Patent number: RE49993
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: June 4, 2024
    Assignee: Logitech Europe S.A.
    Inventors: Marcel Twohig, Yi Hsuan Lin, Anish Shakthi Ovia Selvan, Jean-Christophe Hemes, Jasper Phua, Blaithin Crampton