Patents by Inventor Hsuan Lin

Hsuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11811222
    Abstract: An electrostatic discharge (ESD) protection circuit including a detection circuit, a voltage-divider element, and a discharge element is provided. The detection circuit is coupled between a first power line and a second power line. In response to an ESD event, the detection circuit enables a turn-on signal. The voltage-divider element is coupled between the first power line and a third power line and receives the turn-on signal. The discharge element is coupled between the second and third power lines. In response to the turn-on signal being enabled, the first discharge element discharges an ESD current.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: November 7, 2023
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yeh-Ning Jou, Chieh-Yao Chuang, Hsien-Feng Liao, Ting-Yu Chang, Chih-Hsuan Lin, Chang-Min Lin, Shao-Chang Huang, Ching-Ho Li
  • Patent number: 11810872
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first drain conductive element of the source protective circuit partially overlaps a first source conductive element of the drain protective circuit.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: November 7, 2023
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Jian-Hsing Lee, Shao-Chang Huang, Chih-Hsuan Lin, Yu-Kai Wang, Karuna Nidhi, Hwa-Chyi Chiou
  • Patent number: 11810826
    Abstract: A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yip Loh, Yan-Ming Tsai, Hung-Hsu Chen, Chih-Wei Chang, Sheng-Hsuan Lin
  • Patent number: 11807716
    Abstract: An oligomer (2,6-dimethylphenylene ether) is provided. Its structure is shown as follows: which comprises separately independent hydrogen; alkyl or phenyl; separately independent —NR—, —CO—, —SO—, —CS—, —SO2—, —CH2—, —O—, null, —C(CH3)2—, or and a hydrogen, The features of the cured products include a high glass-transition temperature, a low dielectric feature, preferred thermal stability, and good flame retardancy. The present invention effectively controls the number-average molecular weight of the product to obtain excellent organic solubility.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: November 7, 2023
    Assignee: CPC Corporation, Taiwan
    Inventors: Sheng-De Li, Ching-Hsuan Lin, Yi-Hsuan Hsieh, Wei-Yen Chen, Way-Chih Hsu, Jui-Fu Kao, Ming-Yu Huang, Jann-Chen Lin, Yih-Ping Wang
  • Patent number: 11804269
    Abstract: A flash memory cell includes a rectifying device and a transistor. The rectifying device has an input end coupled to a bit line. The transistor has a charge storage structure. The transistor has a first end coupled to an output end of the rectifying device, the transistor has a second end coupled to a source line, and a control end of the transistor is coupled to a word line.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: October 31, 2023
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Feng-Min Lee, Po-Hao Tseng, Yu-Hsuan Lin, Ming-Hsiu Lee
  • Publication number: 20230339345
    Abstract: A charging system for charging an electric vehicle includes a charging device and a mobile power supplying equipment. The charging device includes a charging base, a power receiving terminal disposed on the charging base, and a charging gun electrically connected to the power receiving terminal and configured to charge the electric vehicle. The mobile power supplying equipment includes a power module, a docking device, and a power supplying terminal disposed on the docking device and electrically connected to the power module. When the mobile power supplying equipment moves to a position within a predetermined range of the charging base, the docking device is configured to adjust the power supplying terminal to make the power supplying terminal detachably dock with the power receiving terminal, and the power module then outputs power to the charging gun for the charging gun charging the electric vehicle.
    Type: Application
    Filed: November 15, 2022
    Publication date: October 26, 2023
    Applicant: National Taipei University of Technology
    Inventors: Leeh-Ter YAO, Chang-Qi ZHANG, Yi-Cheng JIANG, Li-Tung LEE, Yu-Ta HUANG, Kai-Sen CHANG, I-Hsuan LIN, Chien-Yuan CHUNG
  • Publication number: 20230343780
    Abstract: An electrostatic discharge (ESD) protection structure including a P-type substrate, a P-type structure, an N-type buried layer, an element active region, a P-type guard ring, and an N-type structure is provided. The P-type structure is formed in the P-type substrate and serves as an electrical contact of the P-type substrate. The N-type buried layer is formed in the P-type substrate. The element active region is formed on the N-type buried layer. The P-type guard ring is formed on the N-type buried layer and surrounds the element active region. The N-type structure is formed on the N-type buried layer and disposed between the P-type guard ring and the P-type structure.
    Type: Application
    Filed: April 20, 2022
    Publication date: October 26, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chang-Min LIN, Chih-Hsuan LIN, Yeh-Ning JOU, Hwa-Chyi CHIOU, Jian-Hsing LEE
  • Publication number: 20230343637
    Abstract: Multiple dry etching operations are performed to form an opening for an interconnect structure, with a wet cleaning operation performed in between the dry etching operations. This multi-step etch approach increases the effectiveness of residual material removal, which increases the quality of the interconnect structure and reduces the likelihood of under etching, both of which increase semiconductor device yield and semiconductor device performance.
    Type: Application
    Filed: April 25, 2022
    Publication date: October 26, 2023
    Inventors: Ying-Yu LAI, Chih-Yun WANG, Chih-Hsuan LIN, Hsi Chung CHEN
  • Patent number: 11798846
    Abstract: The present disclosure provides embodiments of a semiconductor device. In one embodiment, the semiconductor device includes a gate structure, a source/drain feature adjacent the gate structure, a first dielectric layer over the source/drain feature, an etch stop layer over the gate structure and the first dielectric layer, a second dielectric layer over the etch stop layer, a source/drain contact that includes a first portion extending through the first dielectric layer and a second portion extending through the etch stop layer and the second dielectric layer, a metal silicide layer disposed between the second portion and etch stop layer, and a metal nitride layer disposed between the first portion and the first dielectric layer.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hsuan Lin, Xi-Zong Chen, Chih-Teng Liao
  • Publication number: 20230335600
    Abstract: A method for forming a semiconductor device structure includes forming nanostructures over a substrate. The method also includes forming a work function layer surrounding the nanostructures. The method also includes forming spacers over opposite sides of the work function layer. The method also includes forming a first metal layer over the work function layer and sidewalls of the spacers. The method also includes forming a second metal layer surrounded by the first metal layer. The method also includes etching the first metal layer over opposite sides of the second metal layer. The method also includes forming a cap layer over a top surface and a sidewall of the second metal layer.
    Type: Application
    Filed: April 15, 2022
    Publication date: October 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Lung CHENG, Huang-Hsuan LIN, Chih-Chieh YEH
  • Publication number: 20230336230
    Abstract: A method for performing beamforming sounding feedback in a system-parameter-aware manner and associated apparatus are provided. The method applicable to a wireless transceiver device within a wireless communications system may include: checking a plurality of system parameters of the wireless communications system to generate a plurality of checking results of the plurality of system parameters, respectively, wherein any checking result among the plurality of checking results indicates a current value of a corresponding system parameter among the plurality of system parameters; modifying a first beamforming feedback matrix according to the plurality of checking results to generate a second beamforming feedback matrix; and sending beamforming sounding feedback information carrying the second beamforming feedback matrix to another device within the wireless communications system, for further processing of the other device.
    Type: Application
    Filed: March 13, 2023
    Publication date: October 19, 2023
    Applicant: MEDIATEK INC.
    Inventors: Chun-Ting Lin, Pu-Hsuan Lin, Tsung-Hsuan Wu, Hung-Tao Hsieh, Yi-Cheng Huang, Li-Tien Chang
  • Patent number: 11790990
    Abstract: The application provides a content addressable memory (CAM) memory device, a CAM memory cell and a method for searching and comparing data thereof. The CAM memory device includes: a plurality of CAM memory cells; and an electrical characteristic detection circuit coupled to the CAM memory cells; wherein in data searching, a search data is compared with a storage data stored in the CAM memory cells, the CAM memory cells generate a plurality of memory cell currents, the electrical characteristic detection circuit detects the memory cell currents to generate a plurality of sensing results, or the electrical characteristic detection circuit detects a plurality of match line voltages on a plurality of match lines coupled to the CAM memory cells to generate the plurality of search results; and the storage data is a single-bit multi-level storage data and/or the search data is a single-bit multi-level search data.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: October 17, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Hsuan Lin, Po-Hao Tseng
  • Patent number: 11787904
    Abstract: A phosphinated (2,6-dimethylphenyl ether) oligomer, preparation method thereof and cured product. The phosphinated (2,6-dimethylphenyl ether) oligomer includes a structure represented by Formula (1): wherein X is a single bond, —CH2—, —O—, —C(CH3)2— or R?0, R0, R1, R2 and R3 are independently hydrogen, C1-C6 alkyl or phenyl; n and m are independently an integer from 0 to 300; p and q are independently an integer from 1 to 4; Y is hydrogen, U and V are independently an aliphatic structure.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: October 17, 2023
    Assignee: CPC CORPORATION, TAIWAN
    Inventors: Sheng-De Li, Ching-Hsuan Lin, Cheng-Liang Liu, Jun-Cheng Ye, You-Lin Shih, Yu An Lin, Wei-Yen Chen, Way-Chih Hsu, Jui-Fu Kao, Ming-Yu Huang, Jann-Chen Lin, Yih-Ping Wang
  • Publication number: 20230324781
    Abstract: An illumination system includes a light source module, a first lens array, a condensing element, a second lens array, and a prism element. The light source module is configured to provide an illumination beam. The first lens array is disposed on the transmission path of the illumination beam. The condensing element is disposed on the transmission path of the illumination beam. The first lens array is located between the light source module and the condensing element. The second lens array is disposed on the transmission path of the illumination beam. The prism element is disposed on the transmission path of the illumination beam. The second lens array is located between the condensing element and the prism element, wherein the surface area of the second lens array is greater than the surface area of the first lens array.
    Type: Application
    Filed: March 8, 2023
    Publication date: October 12, 2023
    Applicant: Coretronic Corporation
    Inventors: Meng-Hsuan Lin, Yen-Lin Chen
  • Publication number: 20230323543
    Abstract: Embodiments of the disclosure advantageously provide in situ selectively deposited molybdenum films having reduced resistivity and methods of reducing or eliminating lateral growth of a selectively deposited molybdenum layer. Additional embodiments provide integrated clean and deposition processes which improve the selectivity of in situ selectively deposited molybdenum films on features, such as a via. Further embodiments advantageously provide methods of improving uniformity and selectivity of bottom-up gap fill for vias with improved film properties.
    Type: Application
    Filed: April 6, 2022
    Publication date: October 12, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Tuerxun Ailihumaer, Yixiong Yang, Annamalai Lakshmanan, Srinivas Gandikota, Yogesh Sharma, Pei Hsuan Lin, Yi Xu, Zhimin Qi, Aixi Zhang, Shiyu Yue, Yu Lei
  • Patent number: 11780883
    Abstract: The present invention provides a derived peptide of a lactoferrin, a composition comprising the same and a use thereof for promoting and/or increasing lipid synthesis. The derived peptide of the lactoferrin comprises the amino acid sequence of SEQ ID NO: 01.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: October 10, 2023
    Assignee: RENORIGIN INNOVATION INSTITUTE CO., LTD.
    Inventors: Hsiu-Chin Huang, Hsuan Lin
  • Publication number: 20230315218
    Abstract: An optical navigation device control method comprising: (a) computing brightness contrast information of original images captured by an image sensor of an optical navigation device; (b) computing brightness variation levels of the original images; (c) improving image qualities of the original images based on the brightness contrast information and the brightness variation levels, to generate adjusted images; and (d) computing movements of the optical navigation device based on displacement between the adjusted images. The optical navigation device is located on a surface. The step (d) comprises: collecting reference images of different parts of the surface for a plurality of combinations of moving directions of the optical navigation device and placement directions of the surface; and determining a type of the surface via comparing images of a current surface with the reference images.
    Type: Application
    Filed: May 4, 2023
    Publication date: October 5, 2023
    Applicant: PixArt Imaging Inc.
    Inventors: Bo-Yi Chang, Yao-Hsuan Lin
  • Publication number: 20230317858
    Abstract: A method and device according to the present disclosure includes a substrate that has a first transistor terminal such as a source feature and a second transistor terminal such as another source feature. Contact structures are formed on each source/drain feature. After forming the contact structures, a via opening is formed in dielectric materials above the contact structures, which is filled to form a non-linear via that extends from the contact on the first source feature to the contact on the second source feature. The non-linear via may include an outline in a top view of an undulating-shape having convex and/or concave portions.
    Type: Application
    Filed: July 15, 2022
    Publication date: October 5, 2023
    Inventors: Kuo-Chiang TSAI, Pei-Hsuan LIN, Jeng-Ya YEH, Mu-Chi CHIANG
  • Publication number: 20230310320
    Abstract: The present disclosure provides a soluble microcarrier, including soluble polymer including a plurality of soluble monomers binding to each other with a reducing crosslinking agent. The soluble microcarrier of present disclosure facilitates the attachment of cells, and reducing agents can facilitate the detachment of cells. When the soluble microcarrier is in contact with a reducing agent, the soluble microcarrier degrades.
    Type: Application
    Filed: May 11, 2022
    Publication date: October 5, 2023
    Inventors: Hsieh-Chih TSAI, Shuian-Yin LIN, Ming-Chien YANG, Chun-Chiang HUANG, Yu-Hsuan LIN
  • Patent number: D1002616
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: October 24, 2023
    Assignee: Logitech Europe S.A.
    Inventors: Yi-Hsuan Lin, Blaithin Crampton, Marcel Twohig, Anish Shakthi Ovia Selvan, Anatoliy Polyanker, Jingyan Ma, Ming Feng Hsieh, Olivia Hildebrand