Patents by Inventor Hsuan Lin

Hsuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory device and operation method thereof
    Patent number: 11853890
    Abstract: Provided is an operation method for a memory device, the memory device being used for implementing an Artificial Neural Network (ANN). The operation method includes: reading from the memory device a weight matrix of a current layer of a plurality of layers of the ANN to extract a plurality of neuro values; determining whether to perform calibration; when it is determined to perform calibration, recalculating and updating a mean value and a variance value of the neuro values; and performing batch normalization based on the mean value and the variance value of the neuro values.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: December 26, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chao-Hung Wang, Yu-Hsuan Lin, Ming-Liang Wei, Dai-Ying Lee
  • CONTENT ADDRESSABLE MEMORY DEVICE, CONTENT ADDRESSABLE MEMORY CELL AND METHOD FOR SINGLE-BIT MULTI-LEVEL DATA SEARCHING AND COMPARING
    Publication number: 20230410904
    Abstract: The application provides a content addressable memory (CAM) memory device, a CAM cell and a method for searching and comparing data thereof. The CAM device includes: a plurality of CAM cells; and an electrical characteristic detection circuit coupled to the CAM cells; wherein in data searching, a search data is compared with a storage data stored in the CAM cells, the CAM cells generate a plurality of memory cell currents, the electrical characteristic detection circuit detects the memory cell currents to generate a plurality of sensing results, or the electrical characteristic detection circuit detects a plurality of match line voltages on a plurality of match lines coupled to the CAM cells to generate the plurality of search results; and the storage data is a single-bit multi-level storage data and/or the search data is a single-bit multi-level search data.
    Type: Application
    Filed: September 1, 2023
    Publication date: December 21, 2023
    Inventors: Yu-Hsuan LIN, Po-Hao TSENG
  • NOISE CANCELLATION BASED ON AIRFLOW GENERATOR OPERATIONAL SPEED
    Publication number: 20230400220
    Abstract: In some examples, an electronic device includes an audio output device, an airflow generator to generate an airflow, and a system controller to control an operational speed of the airflow generator. The electronic device further includes an audio controller to generate a noise cancellation audio output based on an indicator of the operational speed of the airflow generator provided from the system controller to the audio controller, and send the noise cancellation audio output to the audio output device to mitigate noise produced by the airflow generator.
    Type: Application
    Filed: June 8, 2022
    Publication date: December 14, 2023
    Inventors: Chao-Wen Cheng, Tsung-Yen Chen, Chien Fa Huang, Wen Shih Chen, Mo-Hsuan Lin
  • Method against infection with symbiotic composition
    Patent number: 11839635
    Abstract: A method against Salmonella typhimurium infection includes using a composition containing cultures of Lactobacillus rhamnosus LRH10 which is deposited at the Deutsche Sammlung von Mikroorganismen and Zellkulturen (DSMZ) GmbH under an accession number DSM 32786, Lactobacillus paracasei LPC12 which is deposited at the DSMZ GmbH under an accession number DSM 32785, Lactobacillus fermentum LF26 which is deposited at the DSMZ GmbH under an accession number DSM 32784, Streptococcus thermophilus ST30 which is deposited at the DSMZ GmbH under an accession number DSM 32788, and Lactobacillus helveticus LH43 which is deposited at the DSMZ GmbH under an accession number DSM 32787.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: December 12, 2023
    Assignee: SYNBIO TECH INC.
    Inventors: Shih-Hsuan Lin, Ai-Hua Hsu, Chia-Chia Lee
  • Multi-Gate Devices And Method Of Forming The Same
    Publication number: 20230395679
    Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, a dielectric feature disposed directly on the substrate and in direct contact with a portion of the vertical stack of channel members, and a source/drain feature disposed directly on the dielectric feature and electrically coupled to a remaining portion of the vertical stack of channel members.
    Type: Application
    Filed: June 3, 2022
    Publication date: December 7, 2023
    Inventors: Ming-Lung Cheng, Huang-Hsuan Lin, Chih Chieh Yeh
  • SYSTEM AND METHOD FOR MEASURING MAGNETIC FIELDS IN PVD SYSTEM
    Publication number: 20230395414
    Abstract: A semiconductor processing system includes a first semiconductor processing site and a second semiconductor processing site. The system includes an unmanned electric vehicle configured to carry a portable cleanroom stocker between the first and second semiconductor processing sites. The portable cleanroom stocker is configured to maintain cleanroom conditions within the portable cleanroom stocker during transportation.
    Type: Application
    Filed: June 3, 2022
    Publication date: December 7, 2023
    Inventors: Mei-Hsuan LIN, Rong Syuan FAN, Jen-Yuan CHANG
  • Semiconductor Devices With Reduced Leakage Current And Methods Of Forming The Same
    Publication number: 20230395669
    Abstract: Semiconductor devices and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece having a channel region, a gate structure over the channel region, gate spacers extending along sidewalls of the gate structure, and an etch stop layer extending along sidewalls of the gate spacers. The method also includes performing an etching process to recess the gate spacers and the gate structure, thereby forming a funnel-shaped trench, depositing a dielectric layer over the workpiece to partially fill the funnel-shaped trench, etching back the dielectric layer to form dielectric spacers on the recessed gate spacers, forming a metal cap on the gate structure without forming the metal cap on the recessed gate spacers, and forming a dielectric cap on the metal cap.
    Type: Application
    Filed: June 4, 2022
    Publication date: December 7, 2023
    Inventors: Yu-Hsuan Lin, Chun Po Chang, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Jian-Hao Chen
  • Portable computing device
    Patent number: 11835982
    Abstract: A portable computing device including a central processing unit (CPU) and a controller is provided. The controller is coupled between the CPU, a graphics processing unit, and a battery module. The controller determines whether to adjust performance of the CPU and the graphics processing unit according to at least one of a battery capacity, a battery power, a battery current, a battery voltage, or a battery temperature of the battery module.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: December 5, 2023
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Hao-Hsuan Lin, Yu-Hsiu Su, Chun-Nan Wang, Jia-Ying Wu, Chia-Sen Chang, Yu-Cheng Shen, Shih-Hsiang Kao
  • Extended side contacts for transistors and methods forming same
    Patent number: 11837603
    Abstract: A method includes forming a source/drain region for a transistor, forming a first inter-layer dielectric over the source/drain region, and forming a lower source/drain contact plug over and electrically coupling to the source/drain region. The lower source/drain contact plug extends into the first inter-layer dielectric. The method further includes depositing an etch stop layer over the first inter-layer dielectric and the lower source/drain contact plug, depositing a second inter-layer dielectric over the etch stop layer, and performing an etching process to etch the second inter-layer dielectric, the etch stop layer, and an upper portion of the first inter-layer dielectric to form an opening, with a top surface and a sidewall of the lower source/drain contact plug being exposed to the opening, and forming an upper source/drain contact plug in the opening.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Yu Lai, Chih-Hsuan Lin, Hsi Chung Chen, Chih-Teng Liao
  • METHOD FOR ADJUSTING TRANSMITTING POWER RATIO OF RADIO MODULE AND ASSOCIATED RADIO SYSTEM
    Publication number: 20230387955
    Abstract: A method for adjusting a transmitting (TX) power ratio of a radio module includes: separating multiple radio modules into multiple radio groups according to a radiofrequency (RF) regulation, wherein the multiple radio modules comprise the radio module; mapping an RF exposure limit to a TX power limit; interacting with at least one other radio module for adjusting the TX power ratio, to obtain at least one adjusted TX power ratio, wherein the radio module and the at least one other radio module are comprised in a same radio group of the multiple radio groups; and adjusting the TX power limit according to the at least one adjusted TX power ratio, to generate an adjusted TX power limit of the radio module.
    Type: Application
    Filed: April 18, 2023
    Publication date: November 30, 2023
    Applicant: MEDIATEK INC.
    Inventors: Fu-Tse Kao, Yi-Hsuan Lin, Han-Chun Chang, Yi-Ying Huang
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THEREOF
    Publication number: 20230387255
    Abstract: A semiconductor structure includes a substrate, a conductive region, a first insulation layer, a second insulation layer, a gate structure, a low-k spacer, a gate contact, and a conductive region contact. The low-k spacer is formed between a sidewall of the gate structure and the first insulation layer. The gate contact is landed on a top surface of the gate structure. A proximity distance between a sidewall of the gate contact and the conductive region contact along a top surface of the second insulation layer is in a range of from about 4 nm to about 7 nm. A method for manufacturing a semiconductor structure is also provided.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Chih-Hsuan Lin, Hsi Chung Chen, Chih-Teng Liao
  • Active array antenna module
    Patent number: 11831078
    Abstract: An active array antenna module includes a cover plate, a metal frame, an antenna main board, a back frame, and a plurality of first fixing structures. The first fixing structures fix the back frame, the metal frame, and the cover plate, so that the antenna main board is fixed between the metal frame and the back frame, so that each of a plurality of antenna units of the antenna main board corresponds to each of a plurality of openings defined by the metal frame and each of a plurality of metal patterns of the cover plate to form a cavity antenna unit, and the active array antenna module includes a plurality of the cavity antenna units.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: November 28, 2023
    Assignee: WANSHIH ELECTRONIC CO., LTD.
    Inventor: Hung-Hsuan Lin
  • Extended Side Contacts for Transistors and Methods Forming Same
    Publication number: 20230378182
    Abstract: A method includes forming a source/drain region for a transistor, forming a first inter-layer dielectric over the source/drain region, and forming a lower source/drain contact plug over and electrically coupling to the source/drain region. The lower source/drain contact plug extends into the first inter-layer dielectric. The method further includes depositing an etch stop layer over the first inter-layer dielectric and the lower source/drain contact plug, depositing a second inter-layer dielectric over the etch stop layer, and performing an etching process to etch the second inter-layer dielectric, the etch stop layer, and an upper portion of the first inter-layer dielectric to form an opening, with a top surface and a sidewall of the lower source/drain contact plug being exposed to the opening, and forming an upper source/drain contact plug in the opening.
    Type: Application
    Filed: August 1, 2023
    Publication date: November 23, 2023
    Inventors: Ying-Yu Lai, Chih-Hsuan Lin, Hsi Chung Chen, Chih-Teng Liao
  • MODEM PERFORMANCE ENHANCEMENT VIA SMART TRANSMISSION POWER DISTRIBUTION
    Publication number: 20230379844
    Abstract: A power-adjusting method for uplink transmission is provided. The power-adjusting method is applied to user equipment (UE). In response to the UE transmitting a first packet carrying a specific message to a network node, the power-adjusting method includes the UE increasing the transmission power to transmit the first packet.
    Type: Application
    Filed: May 23, 2022
    Publication date: November 23, 2023
    Inventors: Chih-Chieh LAI, Yi-Hsuan LIN, Ming-Yuan CHENG, Wei-Yu LAI, Wei-Jen CHEN
  • SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME
    Publication number: 20230378325
    Abstract: Semiconductor device structure and methods of forming the same are described. The structure includes a dielectric layer disposed over an epitaxy source/drain region and a conductive feature disposed in the dielectric layer. The conductive feature includes a metal liner including a first material and a metal fill surrounded by the metal liner. The metal fill includes the first material having a first grain size. The conductive feature further includes a metal cap disposed on the metal liner and the metal fill, and the metal cap includes the first material having a second grain size different from the first grain size.
    Type: Application
    Filed: May 23, 2022
    Publication date: November 23, 2023
    Inventors: Sheng-Hsuan LIN, Feng-Yu CHANG, Shu-Lan CHANG, I Lee, Chun-Yen LIAO
  • Method of Manufacturing Semiconductor Devices with Multiple Silicide Regions
    Publication number: 20230369130
    Abstract: A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Wei-Yip Loh, Yan-Ming Tsai, Hung-Hsu Chen, Chih-Wei Chang, Sheng-Hsuan Lin
  • PROTECTION CIRCUIT
    Publication number: 20230369848
    Abstract: A power detection circuit is provided. The protection circuit is coupled to a pad and includes a trigger circuit and a discharge circuit. The trigger circuit includes a first transistor of a first conductivity type and a second transistor, also of the first conductivity type, which are coupled in series between the pad and a ground terminal. The trigger circuit detects whether a transient even occurs on the pad. The discharge circuit is coupled between the bonding pad and the ground terminal and controlled by the trigger circuit. In response to the transient event occurring on the bonding pad, the trigger circuit generates a trigger voltage to trigger the discharge circuit to provide a discharge path between the pad and the ground terminal.
    Type: Application
    Filed: May 11, 2022
    Publication date: November 16, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Jian-Hsing LEE, Yeh-Ning JOU, Chih-Hsuan LIN, Chang-Min LIN, Hwa-Chyi CHIOU
  • ACTIVE ARRAY ANTENNA MODULE
    Publication number: 20230369777
    Abstract: An active array antenna module includes a cover plate, a metal frame, an antenna main board, a back frame, and a plurality of first fixing structures. The first fixing structures fix the back frame, the metal frame, and the cover plate, so that the antenna main board is fixed between the metal frame and the back frame, so that each of a plurality of antenna units of the antenna main board corresponds to each of a plurality of openings defined by the metal frame and each of a plurality of metal patterns of the cover plate to form a cavity antenna unit, and the active array antenna module includes a plurality of the cavity antenna units.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Inventor: Hung-Hsuan LIN
  • Sounding-interval adaptation using link quality
    Patent number: 11817974
    Abstract: A method for sounding-interval adaptation using link quality for use in an apparatus is provided. The apparatus includes a sounding transceiver. The method includes the following steps: periodically transmitting a sounding packet to a beamformee through a downlink channel from the apparatus to the beamformee according to a first sounding interval; in response to the sounding transceiver receiving a data packet or a report packet from the beamformee, obtaining a current first channel profile from the received data packet or the received report packet; and adaptively adjusting the first sounding interval according to a first mobility indicator which is calculated according to the current first channel profile and the previous first channel profile.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: November 14, 2023
    Assignee: MEDIATEK INC.
    Inventors: Hao-Chih Yu, Pu-Hsuan Lin, Yu-Ting Su
  • METHOD FOR ADJUSTING TRANSMITTING POWER RATIO OF RADIO MODULE AND ASSOCIATED RADIO MODULE
    Publication number: 20230362836
    Abstract: A method for adjusting a transmitting (TX) power ratio of a radio module includes: mapping a radiofrequency (RF) exposure limit to a TX power limit; interacting with at least one other radio module for adjusting the TX power ratio, to obtain an adjusted TX power ratio; and adjusting the TX power limit according to the adjusted TX power ratio, to generate an adjusted TX power limit of the radio module.
    Type: Application
    Filed: April 7, 2023
    Publication date: November 9, 2023
    Applicant: MEDIATEK INC.
    Inventors: Han-Chun Chang, Yen-Wen Yang, Yi-Hsuan Lin