Abstract: A semiconductor device includes a gate electrode, spacers and a hard mask structure. The spacers are disposed on opposite sidewalls of the gate electrode. The hard mask structure includes a first hard mask layer and a second hard mask layer. A lower portion of the first hard mask layer is disposed between the spacers and on the gate electrode, and a top portion of the first hard mask layer is surrounded by the second hard mask layer.

Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

Abstract: This application provides a vehicle and a power battery heating apparatus and method thereof. In the power battery heating method, when a current temperature value of a power battery is lower than a preset temperature value, and a heating condition of the power battery meets a preset condition, a three-phase inverter is controlled to cause a three-phase alternating current motor to generate heat according to heating energy to heat a coolant flowing through the power battery.

Abstract: The present disclosure discloses a motor drive apparatus, a method for controlling the same, a vehicle, and a readable storage medium, where the control method includes: obtaining a required heating power and a required charging power; and adjusting a current value and direction of each phase current of a three-phase motor based on the required heating power, the required charging power, and an output of the motor at a zero torque, to simultaneously control a process of charging a power battery by a power supply module, the torque of the three-phase motor at a zero output, and a three-phase inverter and the three-phase motor to heat a heat exchange medium flowing through at least one of the three-phase inverter or the three-phase motor.

Abstract: The present disclosure provides a vehicle and a power battery heating apparatus and method thereof.

Abstract: The present disclosure provides a power battery charging method, a motor control circuit, and a vehicle. The motor control circuit includes a first switch module, a three-phase inverter, and a control module, where a power supply module, the first switch module, the three-phase inverter, and a three-phase alternating current motor form a current loop, the three-phase alternating current motor inputs or outputs a current by using a wire N extending from a connection point of three phase coils, and the control module controls the three-phase inverter, so that the motor control circuit receives a voltage of the power supply module and outputs a direct current. In the technical solutions, a wire N extends from the three-phase alternating current motor, and further forms different charging loops with the three-phase inverter, the three-phase alternating current motor, and the power battery.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming first and second well regions with different conductivity types in a semiconductor substrate. A well interface is formed between the first and second well regions. The method also includes patterning the semiconductor substrate to form a first fin structure in the first well region, a second fin structure in the second well region, and a first trench between the first and second fin structures. The first trench exposes the well interface in the semiconductor substrate. The method further includes forming insulating spacers on opposite sidewalls of the first trench and etching the semiconductor substrate below the first trench using the insulating spacers as an etch mask, to form a second trench below the first trench. In addition, the method includes filling the first and second trenches with an insulating material.

Abstract: Embodiments of the disclosure provide a semiconductor device including a substrate, an insulating layer formed over the substrate, a plurality of fins formed vertically from a surface of the substrate, the fins extending through the insulating layer and above a top surface of the insulating layer, a gate structure formed over a portion of fins and over the top surface of the insulating layer, a source/drain structure disposed adjacent to opposing sides of the gate structure, the source/drain structure contacting the fin, a dielectric layer formed over the insulating layer, a first contact trench extending a first depth through the dielectric layer to expose the source/drain structure, the first contact trench containing an electrical conductive material, and a second contact trench extending a second depth into the dielectric layer, the second contact trench containing the electrical conductive material, and the second depth is greater than the first depth.

Abstract: Microbial type rhodopsins, such as the light-gated cation-selective membrane channel, channelrhodopsin-2 (Chop2/ChR2) or the ion pump halorhodopsin (HaloR) are expressed in retinal ganglion cells upon transduction using recombinant AAV vectors. Selective targeting of these transgenes for expression in discrete subcellular regions or sites is achieved by including a sorting motif in the vector that can target either the central area or surround (off-center) area of these cells. Nucleic acid molecules comprising nucleotide sequences encoding such rhodopsins and sorting motifs and their use in methods of differential expression of the transgene are disclosed. These compositions and methods provide significant improvements for restoring visual perception and various aspects of vision, particular in patients with retinal disease.

Abstract: A semiconductor device includes a substrate, first and second source/drain features, and a dielectric plug. The substrate has a semiconductor fin. The first and second source/drain features are over first and second portions of the semiconductor fin, respectively. The dielectric plug is at least partially embedded in a third portion of the semiconductor fin. The third portion is in between the first and second portions of the semiconductor fin. The dielectric plug includes a first dielectric material and a second dielectric material different from the first dielectric material.

Abstract: Methods for forming semiconductor structures are provided. The method includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate and patterning the first semiconductor layers and the second semiconductor layers to form a first fin structure. The method further includes forming a first trench in the first fin structure and forming a first source/drain structure in the first trench. The method further includes partially removing the first source/drain structure to form a second trench in the first source/drain structure and forming a first contact in the second trench.

Abstract: The invention provides compositions and kits including at least one nucleic acid or polypeptide molecule encoding for a mutant ChR2 protein. Methods of the invention include administering a composition comprising a mutant ChR2 to a subject to preserve, improve, or restore phototransduction. Preferably, the compositions and methods of the invention are provided to a subject having impaired vision, thereby restoring vision to normal levels.

Abstract: A semiconductor structure includes a first active region over a substrate and extending along a first direction, a gate structure over the first active region and extending along a second direction substantially perpendicular to the first direction, a gate-cut feature abutting an end of the gate structure, and a channel isolation feature extending along the second direction and between the first active region and a second active region. The gate structure includes a metal electrode in direct contact with the gate-cut feature. The channel isolation feature includes a liner on sidewalls extending along the second direction and a dielectric fill layer between the sidewalls. The gate-cut feature abuts an end of the channel isolation feature and the dielectric fill layer is in direct contact with the gate-cut feature.

Abstract: A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.

Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of hybrid fins, a gate, and a dielectric structure. The substrate includes a plurality of fins. The plurality of hybrid fins are respectively disposed between the plurality of fins. The gate covers portions of the plurality of fins and the plurality of hybrid fins. The dielectric structure lands on one of the plurality of hybrid fins to divide the gate into two segment. The two segments are electrically isolated to each other by the dielectric structure and the one of the plurality of hybrid fins.

Abstract: A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.

Abstract: A resistance spot welding method of galvanized high-strength steel with good joint performance, in which three welding pulses are used within one spot welding schedule. The method includes applying a first welding pulse and a second welding pulse which are used for generating a nugget and suppressing the generation of liquid metal embrittlement (LME) cracks, respectively. The first welding pulse generates a nugget having a diameter of 3.75T1/2-4.25T1/2 in which T represents a plate thickness. The second welding pulse causes the nugget to grow at a rate less than a rate of growth during the first welding pulse. A third welding pulse, which is a tempering pulse, is applied for improving plasticity of a welding spot.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a nanostructure disposed over a substrate, wherein the nanostructure includes a plurality of semiconductor layers separated vertically from each other and a dummy pattern layer including dielectric material disposed over and separated vertically from a top semiconductor layer of the plurality of semiconductor layers. The exemplary semiconductor device also comprises a gate structure disposed over a channel region, wherein the gate structure wraps around each of the plurality of semiconductor layers and the dummy pattern layer of the nanostructure.

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, an S/D feature disposed over the semiconductor fin, and a first dielectric fin and a second dielectric fin disposed over the substrate, where the semiconductor fin is disposed between the first dielectric fin and the second dielectric fin, where a first air gap is enclosed by a first sidewall of the epitaxial S/D feature and the first dielectric fin, and where a second air gap is enclosed by a second sidewall of the epitaxial S/D feature and the second dielectric fin.

Abstract: A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a fin structure, a gate electrode, a source-drain region, a plug and a hard mask structure. The gate electrode crosses over the fin structure. The source-drain region in the fin structure is aside the gate electrode. The plug is disposed over and electrically connected to the gate electrode. The hard mask structure surrounds the plug and is disposed over the gate electrode, wherein the hard mask structure includes a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.