Abstract: The present invention relates to a resin composition having a high flow property, low thermal expansion characteristics, and excellent mechanical properties, and a prepreg and a metal clad laminate formed from the same.

Abstract: The present invention relates to a resin composition having high miscibility between internal components, low thermal expansion characteristics, and excellent mechanical properties, and a prepreg and a metal clad laminate formed from the same.

Abstract: A motion assistive apparatus may include a receiver allowing a user to intuitively adjust performance of the motion assistive apparatus and a method of controlling the same. The motion assistive apparatus may include a receiver provided to adjust variable characteristics of the motion assistive apparatus, a processor to adjust a variable parameter related to adjustment of the variable characteristics, in response to adjustment of the variable characteristics through the receiver, and an actuator to output changed assist power in response to adjustment of the variable parameter to change the variable characteristics.

Abstract: A wafer measurement system for measuring a measurable characteristic of a first measurement target formed on a wafer includes: a memory and a processor. The memory is configured to store an image of the wafer, multiple templates each including at least one line, and a measurement program. The processor is accessible to the memory and is configured to execute multiple modules included in the measurement program. The modules include: a template selection module configured to receive the templates and select a measurement template corresponding to a shape of the first measurement target; a template matching module configured to match the measurement template to the first measurement target; and a measurement module configured to measure the measurable characteristic of the first measurement target based on position information of the measurement template.

Abstract: A data processing system includes a plurality of memory boards including a plurality of memory devices, and an error management controller that generates second error information based on plural pieces of first error information respectively received from each of the memory devices, and a memory error analysis device that analyzes the second error information received from the memory boards.

Abstract: A memory device includes an error correction code (ECC) block suitable for performing an ECC operation, and generating a flag signal when an error is detected and corrected through the ECC operation in data read from a memory cell array, and a refresh control block suitable for comparing an active row address with a target address in response to the flag signal, and refreshing data of a neighboring address of the target address based on a comparison result.

Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a first substrate, a second substrate disposed on the first substrate, a stack which is disposed on the second substrate and includes stacked memory cells, and a discharge contact structure electrically coupling the second substrate with the first substrate such that charges in the second substrate are discharged to the first substrate.

Abstract: A method of operating a memory device includes performing a data read operation on at least one victim sub-block within a memory block containing a plurality of sub-blocks therein, in response to an erase command directed to a selected sub-block within the plurality of sub-blocks. Next, a soft program operation is performed on the at least one victim sub-block. This soft programming operation is then followed by an operation to erase the selected sub-block within the plurality of sub-blocks. This operation to erase the selected sub-block may include providing an erase voltage to a bulk region of a substrate on which the memory block extends, and the at least one victim sub-block may be disposed between the selected sub-block and the substrate.

Abstract: The present invention relates to a method and device for generating an engineering topology of a digital substation. The method may include: generating, by a single line diagram generation module, a single line diagram of the digital substation based on input information regarding a plurality of substation component devices and connection relations therebetween; converting, by a topology conversion module, the single line diagram of the digital substation into an engineering topology conforming to international standards by use of conversion conditions stored in a topology component management module; verifying, by a topology verification module, whether the engineering topology is suitable for the digital substation based on the international standards; and generating, by an international standard file generation module, a single line diagram engineering file of the digital substation as a system specification description (SSS) by use of the verified engineering topology.

Abstract: A substrate structure for an image sensor module includes a module substrate including a sensor mounting hole, a reinforcing plate on a lower surface of the module substrate, an image sensor chip on the reinforcing plate within the sensor mounting hole, and a reinforcing pattern in the module substrate. The reinforcing plate covers the sensor mounting hole. An upper surface of the image sensor chip may be exposed by the module substrate. The reinforcing pattern is adjacent to the sensor mounting hole and extends in at least one direction.

Abstract: An analog-digital converter may include: an analog-digital converter comprising: a ramp signal selection unit suitable for receiving ramp signals having different offsets, and sequentially selecting one of the ramp signals according to a preset order; a comparison unit suitable for comparing the magnitudes of the selected ramp signal with a pixel signal, and outputting a comparison signal according to the comparison result; and a counting unit suitable for counting the number of clocks of a clock signal until the comparison signal transitions, and outputting a count signal based on the count when the comparison signal transitions.

Abstract: A light source device using a polarity of a material may include a transparent frame forming an inner space accommodating a nonpolarity material and a polarity material; a light source portion irradiating light through the nonpolarity material or the polar material accommodated in the transparent frame; and an electromagnet configured to switch respective positions of the nonpolarity material and the polar material by a magnetic force generated as a current is applied from outside of the light source device.

Abstract: The present invention relates to a thermosetting resin composition for a semiconductor package and a prepreg using the same. Specifically, a thermosetting resin composition for a semiconductor package which exhibits a low curing shrinkage ratio and has a high glass transition temperature and greatly improved flowability by introducing acrylic rubber and mixing two specific inorganic fillers surface-treated with a binder of a specific composition at a certain ratio, and a prepreg using the same, are provided.

Abstract: A graft for augmentation rhinoplasty, the graft including bone tissue and cartilage tissue, and a method of performing augmentation rhinoplasty by using the graft are disclosed. According to the disclosure, autologous tissue for augmentation rhinoplasty can be obtained in a sufficient amount to so that a nose can be uplifted to a desired height. In addition, rhinoplasy can be easily performed, resulting in a naturally-shaped nose. As the osseous tissue is grafted on the originally existing osseous tissue and cartilage tissue is grafted on the originally existing cartilage, the construction of the original anatomical structure of the nose can be allowed and there is an effect that there is no side effect such as a foreign body reaction.

Abstract: A semiconductor device may be provided. The semiconductor device may include a latch comparison circuit configured for generating a latched address by latching a pattern signal inputted through an address, and generate a comparison signal by comparing a pattern signal inputted through the address and the latched address. The semiconductor device may include a failure flag generation circuit configured for generating a failure flag signal based on the comparison signal.

Abstract: A plasma processing apparatus including an electrostatic chuck supporting a wafer; a focus ring disposed to surround an outer circumferential surface of the wafer; an insulation ring disposed to surround an outer circumferential surface of the focus ring; and an edge ring supporting lower portions of the focus ring and the insulation ring, the edge ring being spaced apart from the electrostatic chuck and surrounding an outer circumferential surface of the electrostatic chuck; wherein the edge ring includes a flow channel containing a fluid therein.

Abstract: An etching effect prediction method includes determining a sample area of a mask pattern in which etch bias is to be predicted, determining input parameters indicating physical characteristics affecting an etching process undertaken in the sample area, comparing an output value obtained by inputting the input parameters to an artificial neural network, to a measured value of the etch bias that occurred in the sample area, and operating the artificial neural network until a difference between the output value and the measured value is equal to or less than a predetermined reference value.

Abstract: The described technology relates to a light detection and ranging (LIDAR) device. The LIDAR device can include a transmitter configured to emit an optical signal, a first lens section configured to convert the optical signal into collimated light, a reflector configured to adjust a direction of the converted optical signal, a second lens section configured to allow the adjusted optical signal to have the same focal plane even though a reflection angle of the reflector is varied and a third lens section configured to convert the optical signal passed through the second lens section into collimated light. The LIDAR device can also include a fourth lens section configured to allow the optical signal, and a receiver configured to receive the optical signal passed through the fourth lens section. The third lens section and the fourth lens section are positioned on the same line in a first direction.

Abstract: Provided are a plasma treatment apparatus and a method of fabricating semiconductor device using the same. The plasma treatment apparatus includes a chamber which provides a plasma treatment space, a bottom electrode disposed in the chamber and supports a wafer, a top electrode disposed in the chamber facing the bottom electrode, a source power source which supplies a source power output of a first frequency to the bottom electrode, a bias power source which supplies a bias power output of a second frequency different from the first frequency to the bottom electrode, and a pulse power source which applies a pulse voltage to the bottom electrode, wherein the bias power output is a bias voltage which is pulse-modulated to a first voltage level in a first time section and pulse-modulated to a second voltage level in a second time section and is applied to the bottom electrode.

Abstract: A semiconductor device includes: a non-volatile memory including a normal region, a self-repair region and a redundancy region, each having a plurality of cells; a first boot-up control block suitable for controlling a first boot-up operation to detect defective cells of the normal region and store a defective address in a first latch unit; a self-program control block suitable for controlling a self-program operation to program the defective address stored in the first latch unit into the self-repair region; and a second boot-up control block suitable for controlling a second boot-up operation to read out data of the normal region based on an input address while reading out data of the redundancy region instead of the data of the normal region when data of the self-repair region coincides with the input address.