Abstract: A data processing system includes: a memory device suitable for performing an operation corresponding to a command and outputting a memory data; a data collecting device suitable for collecting big data by integrating the command and the memory data at a predetermined cycle or at every predetermined time, splitting the collected big data based on a predetermined unit, and transferring the split big data; and a data processing device suitable for storing the split big data received from the data collecting device in block-based files in a High-Availability Distributed Object-Oriented Platform (HADOOP) distributed file system (HDFS), classifying the block-based files based on a particular memory command, and processing the block-based files.

Abstract: A method of evaluating a movement tendency of ions in an electrolyte membrane includes counting inter-movement ions, counting intra-movement ions and calculating the ratio of the intra-movement ions and inter-movement of ions. The movement tendency of ions is predicted based on the ratio. In the case of evaluating a movement tendency of ions using the method, since the structure of the electrolyte membrane in which the ratios of intra-movement and inter-movement are maximized is predicted through measurement of the ratios of the intra-movement and inter-movement of ions, ohmic resistance that may occur in a membrane-electrode assembly (MEA) may be reduced. The electrolyte membrane having the optimal structure predicted by the method can be applied to a fuel cell to increase its performance.

Abstract: An etchant composition may include: a peroxosulfate; a cyclic amine compound; a first amphoteric compound including a carboxyl group; and a second amphoteric compound including a sulfone group, wherein the second amphoteric compound may be different from the first amphoteric compound.

Abstract: A display device includes a substrate corresponding to a display area in which an image is displayed, and a non-display area at at least one side of the display area, a touch sensing device at the display area, first outer lines electrically connected to the touch sensing device, and located at a first non-display area that is a first portion of the non-display area, second outer lines connecting the first outer lines and the touch sensing device, a plurality of pixels at the display area, a driving circuit at the first non-display area for driving the pixels, and a power supply line electrically connected to the pixels and located at a second non-display area that is a second portion of the non-display area.

Abstract: A system of analyzing a crystal defect includes an image processor, an image generator, and a comparator. The image processor processes a measured transmission electron microscope (TEM) image that is provided by capturing an image of a specimen having a crystal structure, to provide structural defect information of the specimen. The image generator provides a plurality of virtual TEM images corresponding to a plurality of three-dimensional structural defects of the crystal structure. The comparator compares the measured TEM image with the plurality of virtual TEM images using the structural defect information to determine a defect type of the measured TEM image.

Abstract: An exposure mask includes a first transmission portion, a second transmission portion, and a blocking portion. The first transmission portion is configured to, when illuminated with light, transmit the light at a first energy level. The first transmission portion is disposed in association with formation of a first contact hole in an underlying layer. The second transmission portion is configured to, when illuminated with the light, transmit the light at a second energy level. The second transmission portion is disposed in association with formation of a second contact hole in the underlying layer. The blocking portion is configured to block the light, and is disposed in association with a boundary region between a first region and a second region of the underlying layer. The second transmission portion is further configured to enable the second contact hole to be formed deeper into the underlying layer than the first contact hole.

Abstract: A program method of a nonvolatile memory device that performs a plurality of program loops is provided. At least one of the plurality of program loops includes dividing a channel of a selected cell string into a first side channel and a second side channel during a first interval and a second interval, turning off a string selection transistor of the selected cell string by applying a string select line voltage of a first level during the first interval, and boosting a first voltage of the first side channel and a second voltage of the second side channel, and turning on the string selection transistor by applying the string select line voltage of a second level different from the first level during the second interval, and performing a hot carrier injection (HCI) program operation on a selected memory cell corresponding to the first side channel or the second side channel.

Abstract: A three-dimensional (3D) memory device having a plurality of vertical channel structures includes a first memory block, a second memory block, and a bit line. The first memory block includes first vertical channel structures extending in a vertical direction with respect to a surface of a substrate. The second memory block includes second vertical channel structures on the first vertical channel structures in the vertical direction and first and second string selection lines extending in a first horizontal direction and offset in the vertical direction. The bit line extends in the first horizontal direction between the first and second memory blocks and is shared by the first and second memory blocks. The second memory block may include first and second string selection transistors which are each connected to the bit line and the first string selection line and have different threshold voltages from each other.

Abstract: A display device includes: a first substrate including a display area and a non-display area disposed; a first semiconductor disposed in the display area; a second semiconductor disposed in the non-display area; a first data conductor overlapping the first semiconductor; a second data conductor overlapping the second semiconductor; a first shielding part overlapping the first semiconductor and disposed on the first data conductor; a second shielding part overlapping the second semiconductor and disposed on the second data conductor; an insulating layer disposed on the first shielding part and the second shielding part, wherein a second thickness of the second shielding part is larger than a first thickness of the first shielding part, and a fourth thickness of a second part of the insulating layer corresponding to the second shielding part is smaller than a third thickness of a first part of the insulating layer corresponding to the first shielding part.

Abstract: A display device includes: a plurality of light emitting elements; a pixel definition layer having a plurality of openings defining positions of the light emitting elements; an encapsulation layer on the light emitting elements and the pixel definition layer; an insulation layer on the encapsulation layer and having a smaller width than a portion of the pixel definition layer between two adjacent openings therein; and a plurality of touch sensing cells on the insulation layer.

Abstract: A three-dimensional (3D) memory device having a plurality of vertical channel structures includes a first memory block, a second memory block, and a bit line. The first memory block includes first vertical channel structures extending in a vertical direction with respect to a surface of a substrate. The second memory block includes second vertical channel structures on the first vertical channel structures in the vertical direction and first and second string selection lines extending in a first horizontal direction and offset in the vertical direction. The bit line extends in the first horizontal direction between the first and second memory blocks and is shared by the first and second memory blocks. The second memory block may include first and second string selection transistors which are each connected to the bit line and the first string selection line and have different threshold voltages from each other.

Abstract: Plasma processing equipment includes a chuck stage for supporting a wafer and including a lower electrode, an upper electrode disposed on the chuck stage, an AC power supply which applies first to third signals having different magnitudes of frequencies to the upper electrode or the lower electrode, a dielectric ring which surrounds the chuck stage, an edge electrode located within the dielectric ring, and a resonance circuit connected to the edge electrode. The resonance circuit includes a filter circuit which allows only the third signal among the first to third signals to pass, and a series resonance circuit connected in series with the filter circuit and having a first coil and a first variable capacitor connected in series and grounded.

Abstract: A program method of a nonvolatile memory device that performs a plurality of program loops is provided. At least one of the plurality of program loops includes dividing a channel of a selected cell string into a first side channel and a second side channel during a first interval and a second interval, turning off a string selection transistor of the selected cell string by applying a string select line voltage of a first level during the first interval, and boosting a first voltage of the first side channel and a second voltage of the second side channel, and turning on the string selection transistor by applying the string select line voltage of a second level different from the first level during the second interval, and performing a hot carrier injection (HCI) program operation on a selected memory cell corresponding to the first side channel or the second side channel.

Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a first substrate, a second substrate disposed on the first substrate, a stack which is disposed on the second substrate and includes stacked memory cells, and a discharge contact structure electrically coupling the second substrate with the first substrate such that charges in the second substrate are discharged to the first substrate.