Abstract: A semiconductor device, a test method, and a system including the same are disclosed, which may relate to a technology for testing open and short states of a pad of a semiconductor device.

Abstract: A memory device includes an error correction code (ECC) block suitable for performing an ECC operation, and generating a flag signal when an error is detected and corrected through the ECC operation in data read from a memory cell array, and a refresh control block suitable for comparing an active row address with a target address in response to the flag signal, and refreshing data of a neighboring address of the target address based on a comparison result.

Abstract: A method of operating a memory device includes performing a data read operation on at least one victim sub-block within a memory block containing a plurality of sub-blocks therein, in response to an erase command directed to a selected sub-block within the plurality of sub-blocks. Next, a soft program operation is performed on the at least one victim sub-block. This soft programming operation is then followed by an operation to erase the selected sub-block within the plurality of sub-blocks. This operation to erase the selected sub-block may include providing an erase voltage to a bulk region of a substrate on which the memory block extends, and the at least one victim sub-block may be disposed between the selected sub-block and the substrate.

Abstract: A memory system and a data processing system including the memory system may manage a plurality of memory devices. For example, the data processing system may categorize and analyze error information from the memory devices, acquire characteristic data from the memory devices and set operation modes of the memory devices based on the characteristic data, allocate the memory devices to a host workload, detect a defective memory device among the memory devices and efficiently recover the defective memory device.

Abstract: An exposure mask includes a first transmission portion, a second transmission portion, and a blocking portion. The first transmission portion is configured to, when illuminated with light, transmit the light at a first energy level. The first transmission portion is disposed in association with formation of a first contact hole in an underlying layer. The second transmission portion is configured to, when illuminated with the light, transmit the light at a second energy level. The second transmission portion is disposed in association with formation of a second contact hole in the underlying layer. The blocking portion is configured to block the light, and is disposed in association with a boundary region between a first region and a second region of the underlying layer. The second transmission portion is further configured to enable the second contact hole to be formed deeper into the underlying layer than the first contact hole.

Abstract: A semiconductor device includes: a non-volatile memory including a normal region, a self-repair region and a redundancy region, each having a plurality of cells; a first boot-up control block suitable for controlling a first boot-up operation to detect defective cells of the normal region and store a defective address in a first latch unit; a self-program control block suitable for controlling a self-program operation to program the defective address stored in the first latch unit into the self-repair region; and a second boot-up control block suitable for controlling a second boot-up operation to read out data of the normal region based on an input address while reading out data of the redundancy region instead of the data of the normal region when data of the self-repair region coincides with the input address.

Abstract: A system of analyzing a crystal defect includes an image processor, an image generator, and a comparator. The image processor processes a measured transmission electron microscope (TEM) image that is provided by capturing an image of a specimen having a crystal structure, to provide structural defect information of the specimen. The image generator provides a plurality of virtual TEM images corresponding to a plurality of three-dimensional structural defects of the crystal structure. The comparator compares the measured TEM image with the plurality of virtual TEM images using the structural defect information to determine a defect type of the measured TEM image.

Abstract: A resin composition, optionally for a semiconductor package, and a prepreg and a metal clad laminate using the same are provided. The resin composition according to the present invention may exhibit excellent flowability although being packed with a high content of an inorganic filler, and may provide a prepreg and a metal clad laminate having excellent adhesive strength for a metal foil, and low relative permittivity and a low dissipation factor.

Abstract: A refrigerator includes a storeroom configured to have a pantry install part. The refrigerator also includes a pantry arranged in the pantry install part. The refrigerator also includes a filter case configured to receive a water filter and arranged in the pantry install part to be covered by the pantry.

Abstract: A semiconductor device includes a control circuit configured to receive a clock and generate first to fourth internal clocks which have different phases, and generate first to fourth masking clocks from a latency signal in synchronization with the first internal clock and the second internal clock depending on a mode signal; and a signal mixing circuit configured to output the first to fourth internal clocks as first to fourth strobe signals during enable periods of the first to fourth masking clocks.

Abstract: According to a method of controlling uniformity of plasma, a first RF driving pulse signal including first RF pulses is generated by pulsing a first RF signal having a first frequency, and a second RF driving pulse signal including second RF pulses is generated by pulsing a second RF signal having a second, lower frequency. The first and second RF driving signals are applied to a top electrode and/or a bottom electrode of a plasma chamber. A harmonic control signal including harmonic control pulses is generated based on timing of the first and second RF pulses. A harmonic component of the first and second RF driving pulse signals is reduced via intermittent activation and deactivation of a harmonic control circuit as controlled by the harmonic control signal. The uniformity of plasma is improved through the control based on timings of the RF driving pulses.

Abstract: A data processing system may include: a host; and a memory system including a plurality of memory units and a controller coupled to the plurality of memory units. The controller may include a memory manager suitable for acquiring characteristic data from serial presence detect (SPD) components in the plurality of memory units when power is supplied, providing the characteristic data to the host, setting an operation mode of each of the plurality of memory units based on the characteristic data, and performing memory training, and the host may perform interface training with the controller.

Abstract: A semiconductor device includes a control circuit configured to receive a clock and generate first to fourth internal clocks which have different phases, and generate first to fourth masking clocks from a latency signal in synchronization with the first internal clock and the second internal clock depending on a mode signal; and a signal mixing circuit configured to output the first to fourth internal clocks as first to fourth strobe signals during enable periods of the first to fourth masking clocks.

Abstract: A method of predicting a shape of a semiconductor device includes implementing a modeled semiconductor shape with respect to a designed semiconductor layout, extracting a plurality of samples by independently linearly combining process variables with respect to the modeled semiconductor shape; generating virtual spectrums with respect to ones of the extracted plurality of samples through optical analysis, indexing the virtual spectrums to produce indexed virtual spectrums, generating a shape prediction model by using the indexed virtual spectrums as an input and the modeled semiconductor shape as an output, and indexing a spectrum measured from a manufactured semiconductor device and inputting the spectrum to the shape prediction model to predict a shape of the manufactured semiconductor device.

Abstract: An etching effect prediction method includes determining a sample area of a mask pattern in which etch bias is to be predicted, determining input parameters indicating physical characteristics affecting an etching process undertaken in the sample area, comparing an output value obtained by inputting the input parameters to an artificial neural network, to a measured value of the etch bias that occurred in the sample area, and operating the artificial neural network until a difference between the output value and the measured value is equal to or less than a predetermined reference value.

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

Abstract: A semiconductor device, a test method, and a system including the same are disclosed, which may relate to a technology for testing open and short states of a pad of a semiconductor device.

Abstract: A semiconductor package includes a package substrate, an image sensor disposed on the package substrate, and a bonding layer disposed between the package substrate and the image sensor, and including a first region and a second region, the second region has a modulus of elasticity lower than that of the first region and is disposed on a periphery of the first region.

Abstract: A three-dimensional (3D) memory device having a plurality of vertical channel structures includes a first memory block, a second memory block, and a bit line. The first memory block includes first vertical channel structures extending in a vertical direction with respect to a surface of a substrate. The second memory block includes second vertical channel structures on the first vertical channel structures in the vertical direction and first and second string selection lines extending in a first horizontal direction and offset in the vertical direction. The bit line extends in the first horizontal direction between the first and second memory blocks and is shared by the first and second memory blocks. The second memory block may include first and second string selection transistors which are each connected to the bit line and the first string selection line and have different threshold voltages from each other.

Abstract: A light detection and ranging (LIDAR) time of flight (TOF) sensor for inputting and outputting simultaneously and 3-dimensional laser scanning system including the same are disclosed. In one aspect, the sensor includes a substrate and a light receiving element array provided on the substrate and including a plurality of light receiving elements. The sensor also includes readout circuits configured to receive electrical signals from the light receiving elements and perform signal processing on the electrical signals. The sensor further includes metal lines disposed on the light receiving element array in parallel, provided to correspond to the number of the light receiving elements, and configured to connect the light receiving elements to the readout circuits in one-to-one correspondence.