Patents by Inventor Jeehwan Kim

Jeehwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Silicon germanium-on-insulator formation by thermal mixing
    Patent number: 10249737
    Abstract: A layer of amorphous silicon is formed on a germanium-on-insulator substrate, or a layer of germanium is formed on a silicon-on-insulator substrate. An anneal is then performed which causes thermal mixing of silicon and germanium atoms within one of the aforementioned structures and subsequent formation of a silicon germanium-on-insulator material.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Joel P. De Souza, Jeehwan Kim, Devendra K. Sadana
  • Porous silicon relaxation medium for dislocation free CMOS devices
    Patent number: 10229857
    Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana
  • Three-dimensional conductive electrode for solar cell
    Patent number: 10230010
    Abstract: A photovoltaic device and method include forming a plurality of pillar structures in a substrate, forming a first electrode layer on the pillar structures and forming a continuous photovoltaic stack including an N-type layer, a P-type layer and an intrinsic layer on the first electrode. A second electrode layer is deposited over the photovoltaic stack such that gaps or fissures occur in the second electrode layer between the pillar structures. The second electrode layer is wet etched to open up the gaps or fissures and reduce the second electrode layer to form a three-dimensional electrode of substantially uniform thickness over the photovoltaic stack.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • Temperature grading for band gap engineering of photovoltaic devices
    Patent number: 10230015
    Abstract: A photovoltaic device includes a p-type layer. An intrinsic layer is formed directly on the p-type layer and includes an interface region extending into the intrinsic layer that includes a gradually decreasing band gap energy going from the p-type layer into the intrinsic layer formed by a graded deposition temperature. An n-type layer is formed directly on the intrinsic layer.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ahmed Abou-Kandil, Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Mohamed Saad, Devendra K. Sadana
  • METHODS AND APPARATUS FOR VERTICALLY STACKED MULTICOLOR LIGHT-EMITTING DIODE (LED) DISPLAY
    Publication number: 20190053347
    Abstract: A method of fabricating a multicolor light-emitting diode (LED) display includes forming a first LED layer on a first release layer comprising a first two-dimensional (2D) material disposed on a first substrate. The first LED layer is configured to emit light at a first wavelength. The method also includes transferring the first LED layer from the first release layer to a host substrate and forming a second LED layer on a second release layer comprising a second 2D material disposed on a second substrate. The second LED layer is configured to emit light at a second wavelength. The method also includes removing the second LED layer from the second release layer and disposing the second LED layer on the first LED layer.
    Type: Application
    Filed: October 10, 2018
    Publication date: February 14, 2019
    Inventors: Kyusang LEE, Wei KONG, Jeehwan KIM
  • Porous silicon relaxation medium for dislocation free CMOS devices
    Patent number: 10204836
    Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: February 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana
  • APPARATUS AND METHODS FOR ELECTRICAL SWITCHING
    Publication number: 20190036021
    Abstract: Electrical switching technologies employ the otherwise undesirable line defect in crystalline materials to form conductive filaments. A switching cell includes a crystalline layer disposed between an active electrode and another electrode. The crystalline layer has at least one channel, such as a line defect, extending from one surface of the crystalline layer to the other surface. Upon application of a voltage on the two electrodes, the active electrode provides metal ions that can migrate from the active electrode to the other electrode along the line defect, thereby forming a conductive filament. The switching cell can precisely locate the conductive filament within the line defect and increase the device-to-device switching uniformity.
    Type: Application
    Filed: September 28, 2018
    Publication date: January 31, 2019
    Inventors: Jeehwan KIM, Shinhyun CHOI
  • Controllable indium doping for high efficiency CZTS thin-film solar cells
    Patent number: 10177269
    Abstract: A photovoltaic device includes a first contact layer formed on a substrate. An absorber layer includes Cu—Zn—Sn—S(Se) (CZTSSe) on the first contact layer. A buffer layer is formed in contact with the absorber layer. Metal dopants are dispersed in a junction region between the absorber layer and the buffer layer. The metal dopants have a valence between the absorber layer and the buffer layer to increase junction potential. A transparent conductive contact layer is formed over the buffer layer.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Talia S. Gershon, Jeehwan Kim, Yun Seog Lee, Teodor K. Todorov
  • MOSFET WITH ULTRA LOW DRAIN LEAKAGE
    Publication number: 20190006466
    Abstract: A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.
    Type: Application
    Filed: August 17, 2018
    Publication date: January 3, 2019
    Inventors: Joel P. de Souza, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • FINFET CMOS with Si NFET and SiGe PFET
    Patent number: 10170372
    Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) device includes growing a SiGe layer on a Si semiconductor layer, and etching fins through the SiGe layer and the Si semiconductor layer down to a buried dielectric layer. Spacers are formed on sidewalls of the fins, and a dielectric material is formed on top of the buried dielectric layer between the fins. The SiGe layer is replaced with a dielectric cap for an n-type device to form a Si fin. The Si semiconductor layer is converted to a SiGe fin for a p-type device by oxidizing the SiGe layer to condense Ge. The dielectric material is recessed to below the spacers, and the dielectric cap and the spacers are removed to expose the Si fin and the SiGe fin.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim
  • MOSFET with ultra low drain leakage
    Patent number: 10164014
    Abstract: A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: December 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • Low resistance contact for semiconductor devices
    Patent number: 10157993
    Abstract: A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type material is formed on or in the p-doped layer. The n-type layer includes ZnO. An aluminum contact is formed in direct contact with the ZnO of the n-type material to form an electronic device.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: December 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser
  • Aluminum-doped zinc oxysulfide emitters for enhancing efficiency of chalcogenide solar cell
    Patent number: 10121920
    Abstract: A photovoltaic device includes a substrate, a first electrode formed on the substrate and a p-type absorber layer including a chalcogenide compound. An n-type layer includes a zinc oxysulfide material having a sulfur content adjusted to match a feature of the absorber layer. A transparent contact is formed on the n-type layer.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Talia S. Gershon, Oki Gunawan, Jeehwan Kim, Yun Seog Lee
  • HETERO-INTEGRATION OF III-N MATERIAL ON SILICON
    Publication number: 20180315591
    Abstract: A hetero-integrated device includes a monocrystalline Si substrate and a trench formed in the substrate to expose a crystal surface at a bottom of the trench. Sidewall dielectric spacers are formed on sidewalls of the trench, and a III-V material layer is formed on the crystal surface at the bottom of the trench and is isolated from the sidewalls of the trench by the sidewall dielectric spacers.
    Type: Application
    Filed: June 21, 2018
    Publication date: November 1, 2018
    Inventors: Can Bayram, Christopher P. D'Emic, Devendra K. Sadana, Jeehwan Kim
  • CONE-SHAPED HOLES FOR HIGH EFFICIENCY THIN FILM SOLAR CELLS
    Publication number: 20180315867
    Abstract: A photovoltaic device includes a substrate having a plurality of hole shapes formed therein. The plurality of hole shapes each have a hole opening extending from a first surface and narrowing with depth into the substrate. The plurality of hole shapes form a hole pattern on the first surface, and the hole pattern includes flat areas separating the hole shapes on the first surface. A photovoltaic device stack is formed on the first surface and extends into the hole shapes. Methods are also provided.
    Type: Application
    Filed: June 20, 2018
    Publication date: November 1, 2018
    Inventors: Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • Apparatus and methods for electrical switching
    Patent number: 10115894
    Abstract: Electrical switching technologies employ the otherwise undesirable line defect in crystalline materials to form conductive filaments. A switching cell includes a crystalline layer disposed between an active electrode and another electrode. The crystalline layer has at least one channel, such as a line defect, extending from one surface of the crystalline layer to the other surface. Upon application of a voltage on the two electrodes, the active electrode provides metal ions that can migrate from the active electrode to the other electrode along the line defect, thereby forming a conductive filament. The switching cell can precisely locate the conductive filament within the line defect and increase the device-to-device switching uniformity.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 30, 2018
    Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Jeehwan Kim, Shinhyun Choi
  • POROUS FIN AS COMPLIANT MEDIUM TO FORM DISLOCATION-FREE HETEROEPITAXIAL FILMS
    Publication number: 20180308691
    Abstract: A method for forming a heteroepitaxial layer includes forming an epitaxial grown layer on a monocrystalline substrate and patterning the epitaxial grown layer to form fins. The fins are converted to porous fins. A surface of the porous fins is treated to make the surface suitable for epitaxial growth. Lattice mismatch is compensated for between an epitaxially grown monocrystalline layer grown on the surface and the monocrystalline substrate by relaxing the epitaxially grown monocrystalline layer using the porous fins to form a relaxed heteroepitaxial interface with the monocrystalline substrate.
    Type: Application
    Filed: June 27, 2018
    Publication date: October 25, 2018
    Inventors: Kangguo Cheng, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • ATOMIC LAYER DEPOSITION FOR PHOTOVOLTAIC DEVICES
    Publication number: 20180261711
    Abstract: A photovoltaic device and method include a substrate, a conductive layer formed on the substrate and an absorber layer formed on the conductive layer from a Cu—Zn—Sn containing chalcogenide material. An emitter layer is formed on the absorber layer and a buffer layer is formed on the emitter layer including an atomic layer deposition (ALD) layer. A transparent conductor layer is formed on the buffer layer.
    Type: Application
    Filed: May 10, 2018
    Publication date: September 13, 2018
    Inventors: JEEHWAN KIM, DAVID B. MITZI, BYUNGHA SHIN, TEODOR K. TODOROV, MARK T. WINKLER
  • ATOMIC LAYER DEPOSITION FOR PHOTOVOLTAIC DEVICES
    Publication number: 20180261710
    Abstract: A photovoltaic device and method include a substrate, a conductive layer formed on the substrate and an absorber layer formed on the conductive layer from a Cu—Zn—Sn containing chalcogenide material. An emitter layer is formed on the absorber layer and a buffer layer is formed on the emitter layer including an atomic layer deposition (ALD) layer. A transparent conductor layer is formed on the buffer layer.
    Type: Application
    Filed: May 10, 2018
    Publication date: September 13, 2018
    Inventors: JEEHWAN KIM, DAVID B. MITZI, BYUNGHA SHIN, TEODOR K. TODOROV, MARK T. WINKLER
  • Hetero-integration of III-N material on silicon
    Patent number: 10056251
    Abstract: A hetero-integrated device includes a monocrystalline Si substrate and a trench formed in the substrate to expose a crystal surface at a bottom of the trench. Sidewall dielectric spacers are formed on sidewalls of the trench, and a III-V material layer is formed on the crystal surface at the bottom of the trench and is isolated from the sidewalls of the trench by the sidewall dielectric spacers.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: August 21, 2018
    Assignee: International Business Machines Corporation
    Inventors: Can Bayram, Christopher P. D'Emic, Devendra K. Sadana, Jeehwan Kim