Abstract: Embodiments of the present application disclose a capacitor and a method for producing a capacitor. The capacitor includes: an electrode layer including a first electrode and a second electrode separated from each other; a laminated structure including n dielectric layer(s) and n+1 conductive layers, where the n dielectric layer(s) and the n+1 conductive layers form a structure that a conductive layer and a dielectric layer are adjacent to each other, and the laminated structure forms at least two columnar structures, and n is a positive integer; and an interconnection structure configured to electrically connect an odd-numbered conductive layer in the n+1 conductive layers to the first electrode and electrically connect an even-numbered conductive layer in the n+1 conductive layers to the second electrode. According to the technical solution of the embodiments of the present application, capacitance density of the capacitor could be improved.

Abstract: Embodiments of the present application provide a memristor electrode material preparation method and apparatus, and a memristor electrode material. The preparation method includes: depositing a metal nitride on a substrate by a reactive sputtering process to obtain a metal nitride substrate; and subjecting the metal nitride substrate to laser annealing treatment in a nitrogen-containing atmosphere to nitride an unreacted metal on the metal nitride substrate, so as to obtain a memristor electrode material.

Abstract: The silicon waveguides consist of an input waveguide and an output waveguide, and the input and output silicon waveguides are arranged on the both sides of the Luneburg lens, respectively. The width of the input waveguide is larger than that of the output waveguide. The structure of the Luneburg lens is a metamaterial layer of the periodic silicon nanorod antenna array, which the upper cladding and the lower cladding are SiO2. The required refractive index distributions by the Luneburg lens can be implemented through the metamaterial structure of the gradient index profiles.

Abstract: A PCD may include an active heat transfer system configured to transfer heat from the PCD to a docking device. The active heat transfer system may include a thermoelectric cooler, a heat pipe, or other heat transfer elements. The active heat transfer system may, based on temperature measurements, be activated when the PCD is coupled to the docking device.

Abstract: An embodiment of the present application relates to a trench capacitor and a method for manufacturing the same. The method for manufacturing the capacitor includes: fabricating a trench reaching a depth of a middle insulating layer on a semiconductor layer of an SOI substrate; and further growing an epitaxial layer of the semiconductor layer on a sidewall of the trench by selective epitaxial growth technology so as to further reduce a width of the trench; filling the trench with an electrically insulating material; and finally, fabricating two electrodes of the capacitor separately through a surface electrode. According to a trench capacitor and a method for manufacturing the same provided in an embodiment of the present application, a process flow is simple, and the capacitor manufactured has two advantages of high capacitance density and high breakdown voltage.

Abstract: A capacitor is disclosed, including: a semiconductor substrate including opposite upper and lower surfaces; one first trench disposed in the semiconductor substrate and formed downward from the upper surface; one second trench disposed in the substrate and corresponding to the first trench, and formed upward from the lower surface; a first conductive layer disposed above the substrate and in the first trench; a first insulating layer disposed between the substrate and the first conductive layer; a second conductive layer disposed on the substrate and in the first trench, the second conductive layer being electrically connected to the substrate; a second insulating layer disposed between the second conductive layer and the first conductive layer; a third conductive layer disposed below the substrate and in the second trench; and a third insulating layer disposed between the third conductive layer and the substrate, which is electrically connected to the first conductive layer.

Abstract: A system for estimating front side overlay on a sample based on shape data is disclosed. The system includes a characterization sub-system and a controller. The controller includes one or more processors configured to: generate a vacuum hole map of a vacuum chuck; generate a vacuum force distribution across a sample based on the generated vacuum hole map of the vacuum chuck; determine shape data of the sample based on the vacuum force distribution and an identified relationship between backside surface roughness and vacuum force of the vacuum chuck; and convert the shape data of the sample to an overlay value of a frontside surface of the sample.

Abstract: An optical sensing circuit includes a first light sensor, a second light sensor, a third light sensor, a capacitor, and a sampling circuit. The first light sensor, the second light sensor, and the third light sensor are respectively covered by a first color filter, a second color filter, and a third color filter. The first light sensor is coupled to the capacitor, the sampling circuit, and the third light sensor. The second light sensor is coupled to the first light sensor and is configured to receive a first sensing signal. The third light sensor is coupled between the first light sensor and a voltage source.

Abstract: A method for fabricating a double-sided capacitor is disclosed, which includes: etching trenches having depths not reaching an intermediate insulating layer and trench structures having depths exceeding the intermediate insulating layer on both sides of a silicon-on-insulator (SOI) substrate; and sequentially depositing an insulating dielectric film and a conductive material on surfaces of the trenches and the trenches, then removing insulating material at a bottom of the trenches and the trenches are filled with the conductive material to form conductive channels. The upper conductive channel of the SOI substrate is insulated from an upper layer and is electrically connected to a lower layer; and the lower conductive channel is insulated from the lower layer and is electrically connected to the upper layer.

Abstract: An e-fuse and a manufacturing method thereof, and a memory cell are provided. The method includes: providing a semiconductor substrate including a preset active region; forming an isolating region on the substrate, where the isolating region and the preset active region have a height difference and are connected by at least one side wall; forming a negative electrode and a positive electrode on the preset active region; and forming a fuse link on the side wall for connecting the negative electrode and the positive electrode. Accordingly, the line width of the fuse link is out of the limitation of the limit line width of the semiconductor process, the actual line width of the e-fuse may be smaller than the limit line width of the semiconductor process, and low fusing current is required for fusing.

Abstract: An automatic power switching system includes a first power interface module coupled to a first power supply terminal for obtaining a first power signal, a second power interface module coupled to a second power supply terminal for obtaining a second power signal, a power input identification module for identifying whether the first power signal meets a requirement, a power output module for receiving the first power signal or the second power signal and for providing a corresponding power signal to a power consumption module, and a switch module for turning on the second power interface module and the power output module when confirming the first power signal not meeting the requirement.

Abstract: Provided are an apparatus and a method of fingerprint identification and a terminal device, the fingerprint identification apparatus including: an optical sensor including a pixel array, the pixel array includes a plurality of first type of pixel points and at least one second type of pixel point, the plurality of first type of pixel points and the at least one second type of pixel point are configured to receive optical signals from an object; a color filter layer or a polarizer plate disposed above the at least one second type of pixel point; an intensity of an optical signal received by the at least one second type of pixel point and an intensity of an optical signal received by at least one first type of pixel point adjacent to the at least one second type of pixel point are used to determine whether the object is a real finger.

Abstract: Embodiments of the application provide a capacitive apparatus and a method for producing the same. The capacitive apparatus includes at least one capacitor; where the at least one capacitor includes at least one first dielectric layer and at least one second dielectric layer, the first dielectric layer has a positive voltage coefficient and the second dielectric layer has a negative voltage coefficient; and/or the first dielectric layer has a positive temperature coefficient and the second dielectric layer has a negative temperature coefficient. Using a principle of positive and negative cancellation, when the at least one capacitor is regarded as a whole, a voltage coefficient and/or a temperature coefficient thereof may be zero or close to zero. Thus, when a bias voltage or a temperature of the at least one capacitor changes, a capacitance value thereof does not change or changes slightly, thereby effectively ensuring the performance of the capacitive apparatus.

Abstract: An optical path modulator, applied to a fingerprint identification apparatus, is configured to direct reflected light reflected back from a surface of a finger to an optical detection unit disposed below the optical path modulator, and the optical detection unit is configured to detect the received reflected light, where an array of through holes is arranged between an upper surface and a lower surface of the optical path modulator, and the array of through holes includes a plurality of tilt through holes, where each tilt through hole has a tilt angle greater than 0°, and the tilt angle is an angle between an axial direction of the tilt through hole and a normal direction perpendicular to a surface of the optical path modulator. In a case of the same hole depth, a thinner optical path modulator can be obtained.

Abstract: A security chip includes: a first dielectric layer; a second dielectric layer disposed on the first dielectric layer, where the first dielectric layer is an optically denser medium relative to the second dielectric layer, and a roughness of an upper surface of the first dielectric layer is greater than or equal to a preset threshold, so that light entering the second dielectric layer from the first dielectric layer is able to be totally reflected and/or scattered; and a semiconductor chip disposed on the second dielectric layer. Based on the above technical solution, light incident from a lower surface of the first dielectric layer is able to be totally reflected or scattered by the upper surface of the first dielectric layer, so that most of light cannot reach a logic or storage area on the front of the security chip, thereby achieving the purpose of resisting a laser attack.

Abstract: Present disclosure provide a capacitor includes: a semiconductor substrate; a laminated structure including n conductive layers and m dielectric layer(s), the i-th conductive layer being provided with at least one i-th isolation trench, the (i+1)-th conductive layer being provided above the i-th conductive layer and in the i-th isolation trench, isolation trenches in odd-numbered and even-numbered conductive layers having a first and a second overlap region in a vertical direction respectively, and the first overlap region not overlapping the second overlap region, where m, n, and i are positive integers, n?2, and 1?i?n?1; at least one first external electrode electrically connected to all odd-numbered conductive layer(s) through a first conductive via structure in the second overlap region; and at least one second external electrode electrically connected to all even-numbered conductive layer(s) through a second conductive via structure in the first overlap region.

Abstract: A capacitor and a method of fabricating the capacitor are provided. The capacitor includes a structure for forming a three-dimensional capacitor, the structure being a pillar structure or a trench structure; where when the structure is a pillar structure, the aspect ratio of the pillar structure is more than 10; when the structure is a trench structure, the capacitor further includes a substrate, the trench structure is formed by a material layer disposed on the surface of a base trench of the substrate, and the aspect ratio of the trench structure is more than 10. The aspect ratio of the pillar structure of the capacitor or the aspect ratio of the trench structure may be more than 10, so that the performance of the capacitor is better.

Abstract: Some embodiments provide a method that receives a request for information regarding a path between endpoints of a logical network. The method provides, for display, a visualization of the path including (i) a set of logical network components between the endpoints and (ii) a set of physical network components that implement the logical network components. The physical network components and the logical network components are aligned in the display. In some embodiments, the method receives data regarding a packet tracing operation between the endpoints. The method generates a display including (i) a visualization of the path between the endpoints of the logical network and (ii) a representation of the received data regarding the packet tracing operation, with the packet tracing operation data is visually linked to the components of the path.

Abstract: A capacitor includes a first electrode (1111) and a second electrode (1112); a laminated structure (160) including a first conductive layer, at least one dielectric layer (162, 164) and at least one second conductive layer (163, 165), where the first conductive layer includes at least one groove-shaped support (1611), the at least one dielectric layer and the at least one second conductive layer cover the at least one groove-shaped support, and the first conductive layer, the at least one dielectric layer and the at least one second conductive layer form a structure that a dielectric layer and a conductive layer are adjacent to each other; and an interconnection structure (190) configured to at least connect the first electrode and the second electrode to two adjacent conductive layers respectively.