Patents by Inventor Kei Murayama

Kei Murayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100231444
    Abstract: A positioning receiver and method in which the time required for signal acquisition can be reduced and positioning time can be reduced by increasing the occasion of the signal acquisition. In an SPS receiver mounted user equipment (100), a Doppler shift amount measuring means (112a) of a frequency search range control unit (112) measures the Doppler shift amount of the signals from a plurality of base stations of a communication network. A search range control means (112b) calculates the difference between the maximum value and minimum value of the measured Doppler shift amount of the base stations and determines the search range at the time of satellite signal search by comparing the difference and a predetermined threshold. The search range control means (112b), if it is judged that the difference between the maximum value and minimum value of the Doppler shift amount is larger than the threshold, sets the search range larger and, if not, sets the search range less.
    Type: Application
    Filed: April 26, 2007
    Publication date: September 16, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Akifumi Miyano, Hiroshi Katayama, Kazuhiro Nojima, Hirofumi Yoshida, Kei Murayama
  • Patent number: 7794112
    Abstract: It is a lighting apparatus 10 that has a light emitting element 16, a light emitting element housing 15 having a concave portion 28 that accommodates the light emitting element 16, and an optically transparent member 18 that airproofs a space B formed by the concave portion 28 and transmits light emitted from the light emitting element 16. The concave portion 28 is shaped to become wider toward the optically transparent member 18 from the bottom surface 28A of the concave portion 28. The lighting apparatus 10 is provided with a light shielding member 12 for shielding a part of light emitted from the light emitting element 16 is provided on the optically transparent member 18.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: September 14, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Mitsutoshi Higashi, Kei Murayama, Yuichi Taguchi, Masahiro Sunohara, Akinori Shiraishi
  • Patent number: 7795140
    Abstract: A method of manufacturing a substrate, includes: (a) forming the through hole by etching the silicon substrate from a first surface of the silicon substrate by a Bosch process; (b) forming a thermal oxide film such that the thermal oxide film covers the first surface of the silicon substrate, a second surface of the silicon substrate opposite to the first surface, and a surface of the silicon substrate corresponding to a side surface of the through hole, by thermally oxidizing the silicon substrate where the through hole is formed; (c) removing the thermal oxide film; (d) forming an insulating film such that the insulating film covers the first and second surfaces of the silicon substrate and the surface of the silicon substrate corresponding to the side surface of the through hole; and (e) forming the through electrode in the through hole on which the insulating film is formed.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: September 14, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yuichi Taguchi, Akinori Shiraishi, Masahiro Sunohara, Kei Murayama, Hideaki Sakaguchi, Mitsutoshi Higashi
  • Publication number: 20100207218
    Abstract: A method of manufacturing an electronic component device, includes the steps of preparing a wiring substrate, which includes a silicon substrate, a concave portion provided on its upper surface side, a through hole formed to penetrate the silicon substrate on a bottom surface side of the concave portion, an insulating layer formed on the silicon substrate, a penetration electrode constructed by a lower conductor portion formed to a halfway position of a height direction from a bottom portion of the through hole and a connection metal member (indium layer) formed on the lower conductor portion in the through hole, and an electronic component having a terminal metal member (gold bump) on a lower surface side, and softening the connection metal member of the wiring substrate in a heating atmosphere and then sticking the terminal metal member of the electronic component into the connection metal member and connecting thereto.
    Type: Application
    Filed: February 11, 2010
    Publication date: August 19, 2010
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yuichi TAGUCHI, Akinori Shiraishi, Mitsutoshi Higashi, Kei Murayama
  • Patent number: 7777349
    Abstract: A plurality of quadrilateral-shaped semiconductor elements are stacked on the one surface of a circuit substrate. A side surface wiring for making electrical connection between each of the electrode terminals of the semiconductor elements and a pad formed on the circuit substrate is formed by applying a conductive paste containing conductive particles. A metal wire whose one end is connected to the electrode terminal is extended along a tapered surface formed by cutting off an edge of the electrode terminal surface on which the electrode terminal is formed among edges formed along each of the sides of the semiconductor element. At least a part of the metal wire extended from each of the electrode terminals of the semiconductor elements to the tapered surface is electrically connected to the side surface wiring.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: August 17, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kei Murayama, Shigeru Mizuno, Takashi Kurihara, Akinori Shiraishi, Mitsutoshi Higashi
  • Publication number: 20100133677
    Abstract: A plurality of chip sealing bodies stacked on a wiring substrate with a connection terminal. The chip sealing body includes a semiconductor chip having a semiconductor integrated circuit, a pad and a conductive connecting material, and a resin sealing the semiconductor chip. The chip sealing body is shaped into a cubic form in which a portion of the conductive connecting material except an end portion located on an external device side and all surfaces of semiconductor chip is sealed by the resin and the end portion of the conductive connecting material located on the external device side is exposed from the cubic form. A conductive bonding wire connects the end portions of the conductive connecting materials and the connection terminal respectively. A resin sealing material seals the plurality of chip sealing bodies, the conductive bonding wire, and the wiring substrate.
    Type: Application
    Filed: November 25, 2009
    Publication date: June 3, 2010
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kei Murayama, Akinori Shiraishi, Mitsuhiro Aizawa
  • Patent number: 7708613
    Abstract: A method of producing a light emitting apparatus including a light emitting element, a light emitting element housing having a recess for housing the light emitting element, and a translucent substrate placed on the light emitting element housing is disclosed. The disclosed method includes a fluorescent-substance-containing resin forming step of forming a fluorescent-substance-containing resin on a first side of the translucent substrate which first side is opposite to a second side of the translucent substrate which second side faces the recess. In the fluorescent-substance-containing resin forming step, luminance and chromaticity of light that is emitted from the light emitting element and then transmitted by the fluorescent-substance-containing resin are measured and a thickness of the fluorescent-substance-containing resin is adjusted based on the measured luminance and chromaticity so that light emitted from the light emitting apparatus attains the specified luminance and chromaticity.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: May 4, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yuichi Taguchi, Masahiro Sunohara, Hideaki Sakaguchi, Akinori Shiraishi, Naoyuki Koizumi, Kei Murayama, Mitsutoshi Higashi
  • Patent number: 7705451
    Abstract: A semiconductor device includes a laminated substrate formed by laminating a plurality of semiconductor substrates, a concave part formed in the laminated substrate, and a semiconductor element mounted in the concave part. A method of manufacturing a semiconductor device includes a first step of forming a laminated substrate by laminating a plurality of semiconductor substrates, a second step of forming a concave part by etching the laminated substrate, and a third step of mounting a semiconductor element in the concave part.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: April 27, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kei Murayama, Yuichi Taguchi, Naoyuki Koizumi, Masahiro Sunohara, Akinori Shiraishi, Mitsutoshi Higashi
  • Publication number: 20100099434
    Abstract: A signal capturing apparatus and a signal capturing method wherein the timing at which to implement the clock frequency correction of a GPS reception part during position determination can be optimized to prevent any search omissions, while shortening the time period required for the position determination. A cellular clock precision estimating function part (120) estimates a reception quality of wireless communication. When an estimated reception quality is equal to or greater than a predetermined threshold value, a corrected timing deciding part (140) implements a GPS clock frequency correction with the cellular clock used as a reference. When the reception quality is less than the predetermined threshold value, the corrected timing deciding part (140) inhibits the GPS clock frequency correction from being implemented with the cellular clock used as a reference.
    Type: Application
    Filed: March 29, 2007
    Publication date: April 22, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Kei Murayama, Kazuhiro Nojima, Akifumi Miyano, Hirofumi Yoshida, Hiroshi Katayama
  • Publication number: 20100096163
    Abstract: A wiring board comprises a first pad which is provided on a first surface side of a substrate and on which a first electronic component is to be mounted, and a second pad which is provided on the first surface side of the substrate and on which a second electronic component having a larger amount of heat generation in an operation than that of the first electronic component is to be mounted, a first through electrode which penetrates the substrate and has one of ends connected electrically to the first pad, a second through electrode which penetrates the substrate and has one of ends connected electrically to the second pad, a through trench penetrating the substrate in a portion positioned between a first mounting region for the first electronic component and a second mounting region for the second electronic component, and a heat intercepting member provided in the through trench.
    Type: Application
    Filed: October 20, 2009
    Publication date: April 22, 2010
    Applicant: Shinko Electric Industries Co., Ltd.
    Inventors: Hideaki SAKAGUCHI, Kei Murayama
  • Publication number: 20100085251
    Abstract: A positioning receiver in which the circuit configuration of the receiving system corresponding to a plurality of positioning systems can be simplified and the current consumption and circuit size of which can be reduced. A positioning receiver (100) comprises first low-pass filters (111, 121) which limit outputs of a first signal mixer (103) and a second signal mixer (104) to a first bandwidth, and second low-pass filters (112, 122) which are provided on the output side of the first low-pass filters (111, 121) and limit the outputs of the first low-pass filters (111, 121) to a second bandwidth narrower than the first bandwidth and sets the filter bandwidth of the first low-pass filters (111, 121) greater than that of the second low-pass filters (112, 122).
    Type: Application
    Filed: March 7, 2007
    Publication date: April 8, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Hiroshi Katayama, Akifumi Miyano, Hirofumi Yoshida, Kei Murayama, Kazuhiro Nojima
  • Patent number: 7691673
    Abstract: An electronic parts packaging structure of the present invention includes a wiring substrate having a wiring pattern, a first insulating film which is formed on the wiring substrate and which has an opening portion in a packaging area where an electronic parts is mounted, the electronic parts having a connection terminal flip-chip mounted on the wiring pattern exposed in the opening portion of the first insulating film, a second insulating film for covering the electronic parts, a via hole formed in a predetermined portion of the first and second insulating films on the wiring pattern, and an upper wiring pattern formed on the second insulating film and connected to the wiring pattern through the via hole.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: April 6, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Kei Murayama, Toshinori Koyama, Kazutaka Kobayashi, Mitsutoshi Higashi
  • Patent number: 7655956
    Abstract: There is provided a semiconductor device mounted with a light emitting element, which can be downsized easily, improve light emitting efficiency and be formed easily, and a method for manufacturing the semiconductor device effectively. The semiconductor device includes a substrate, a light emitting element mounted on the substrate by flip chip bonding, a sealing structure sealing the light emitting element and a phosphor film which is formed on an internal surface of the sealing structure. The sealing structure includes a blocking portion which is formed integrally with the substrate so as to surround the light emitting element on the substrate and functions as a reflector that reflects a light emitted from the light emitting element and a cover portion which is arranged on the top of the blocking portion and is bonded to the blocking portion.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: February 2, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Mitsutoshi Higashi, Yuichi Taguchi, Hideaki Sakaguchi, Akinori Shiraishi, Naoyuki Koizumi, Kei Murayama
  • Publication number: 20090300911
    Abstract: A method of manufacturing a wiring substrate comprises the steps of attaching a semiconductor chip to a chip positioning plate of a chip tray formed of silicon, executing wiring formation processing using the semiconductor chip attached to the chip positioning plate as a base point, and detaching the wiring-formed wiring substrate from the chip positioning plate. The chip positioning plate comprises a receiving part for receiving the semiconductor chip, and elastic members respectively disposed in two adjacent surfaces of four surfaces constructing an inside surface of the receiving part, and each of these elastic members exerts pressing force toward directions of opposite surfaces, and the semiconductor chip is pinched between each of the opposite surfaces corresponding to each of the elastic members.
    Type: Application
    Filed: June 4, 2009
    Publication date: December 10, 2009
    Applicant: Shinko Electric Industries Co., Ltd.
    Inventors: Mitsutoshi Higashi, Kei Murayama, Masahiro Sunohara, Hideaki Sakaguchi
  • Patent number: 7622747
    Abstract: A light emitting device is disclosed. The light emitting device includes a light emitting element (15), and a light emitting element container (11) having a concave section (20) for containing the light emitting element (15). The concave section (20) includes a side surface (20A) and a bottom surface (20B) almost orthogonal to the side surface (20A). The light emitting device further includes a conductive paste layer (17) formed of a conductive paste in which metal particles are dispersed in a solution, and the conductive paste layer (17) includes a slanting surface (17A) on the side surface (20A) and the bottom surface (20B).
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: November 24, 2009
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yuichi Taguchi, Hideaki Sakaguchi, Naoyuki Koizumi, Mitsutoshi Higashi, Akinori Shiraishi, Masahiro Sunohara, Kei Murayama
  • Publication number: 20090284276
    Abstract: A probe card is disclosed that includes a board having a first surface and a second surface facing away from each other and a through hole formed between the first and second surfaces; and a probe needle having a penetration part and a support part. The penetration part is placed in the through hole without contacting the board and projects from the first and second surfaces of the board. The support part is integrated with a first one of the end portions of the penetration part and connected to one of the first and second surfaces of the board. The support part has a spring characteristic. The penetration part is configured to have a second one of its end portions come into contact with an electrode pad of a semiconductor chip at the time of conducting an electrical test on the semiconductor chip.
    Type: Application
    Filed: May 13, 2009
    Publication date: November 19, 2009
    Inventors: Yuichi TAGUCHI, Akinori Shiraishi, Masahiro Sunohara, Kei Murayama, Hideaki Sakaguchi
  • Publication number: 20090283914
    Abstract: A method for manufacturing a silicon interposer, includes a step of forming a protection film on a surface, on which an element portion is formed, of a silicon wafer, a step of forming open holes according to planar arrangements of through holes which pass through the silicon wafer in a thickness direction, a step of forming the through holes by etching the silicon wafer using the protection film as a mask, a step of forming an oxide film on inner wall surfaces of the through holes by a thermal oxidation, a step of forming a contact hole, which is in communication with the element portion, in the protection film, and a step of forming wirings on both surfaces of the silicon wafer. In the step of forming the wirings, one of the wirings is formed to be connected electrically to the element portion via a contact portion formed in the contact hole.
    Type: Application
    Filed: May 14, 2009
    Publication date: November 19, 2009
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kei Murayama
  • Publication number: 20090250257
    Abstract: An electronic parts packaging structure of the present invention includes a core substrate having such a structure that a recess portion is provided by forming a prepreg insulating layer having an opening portion therein on a resin layer, and an electronic parts mounted on a bottom portion of the recess portion of the core substrate such that a connection pad of the electronic parts is directed upward, and also, such a structure may be employed that the electronic parts is embedded in a resin layer of a core substrate having a structure that the resin layer is formed on the prepreg insulating layer.
    Type: Application
    Filed: June 8, 2009
    Publication date: October 8, 2009
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Masahiro Sunohara, Kei Murayama, Hiroyuki Kato, Syoji Watanabe
  • Publication number: 20090242107
    Abstract: A method includes the steps of providing a first tape base material on a single side of a stiffener substrate, forming, on the stiffener substrate, a cavity for accommodating a semiconductor chip therein, inserting the stiffener substrate in the cavity and providing the stiffener substrate on the first tape base material, sealing the semiconductor chip and the stiffener substrate with a sealing resin, and removing the first tape base material and forming a build-up layer on a tape removing surface.
    Type: Application
    Filed: March 24, 2009
    Publication date: October 1, 2009
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Masahiro Sunohara, Kei Murayama, Mitsutoshi Higashi, Hideaki Sakaguchi
  • Publication number: 20090236024
    Abstract: A method of manufacturing a wiring substrate is disclosed. The method includes: (a) preparing a supporting substrate including a main body and a through electrode penetrating the main body, wherein the supporting substrate includes a first surface and a second surface opposite to the first surface, and a trace is formed on the second surface of the supporting substrate; (b) forming a build-up wiring structure by alternately forming a wiring layer and an insulating layer on the first surface of the supporting substrate; and (c) obtaining a wiring substrate by separating the build-up wiring structure from the supporting substrate. Step (b) includes: forming the wiring layer using the through electrode as a power feeding wiring, and step (c) includes: peeling the build-up wiring structure from the supporting substrate to obtain the wiring substrate.
    Type: Application
    Filed: March 13, 2009
    Publication date: September 24, 2009
    Applicant: Shinko Electric Industries Co., Ltd.
    Inventors: Mitsutoshi HIGASHI, Kei Murayama, Masahiro Sunohara, Hideaki Sakaguchi