Patents by Inventor Kun Huang

Kun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11501031
    Abstract: The present invention belongs to the field of processing residual stress, and discloses a method for calculating processing parameters for residual stress control by parameter inversion. This method comprises: (a) extracting a characteristic index reflecting the residual stress distribution characteristic from a residual stress distribution curve; (b) respectively presetting initial values of processing parameters for residual stress control, calculating an initial value of the characteristic index, and drawing curves of the characteristic index over the respective processing parameters to obtain respective fitted curves; (c) respectively establishing a relation formula between respective characteristic index increment of the processing parameters and the fitting curve; and (d) assigning the values and performing inversion calculation to obtain the required processing parameters.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: November 15, 2022
    Assignee: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Wenyu Yang, Kun Huang, Yi Gao, Shuo Qiu, Tao Wang, Guangdong Cheng, Kun Yang
  • Patent number: 11489750
    Abstract: An automatic test device is disclosed. The automatic test device is includes connection ports, a processor, and a transmission integrated interface. The connection ports is configured to couple to a device under test. The processor is coupled to the connection ports and is configured to transmit a test instruction through the connection ports to the device under test. The device under test is in a test mode after receiving the test instruction, and the first processor is configured to receive a test signal transmitted through the connection ports from the device under test when the device under test is in the test mode. The transmission integrated interface is coupled between the connection ports and the processor, and is configured to transmit at least one of the test instructions to the connection ports or the processor. An automatic test system is also disclosed herein.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: November 1, 2022
    Assignee: AmTRAN Technology Co., Ltd.
    Inventors: Chin-Kun Huang, Yu-Ruei Li, Peng-Ta Chiu
  • Publication number: 20220336588
    Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a body contact, a gate, a source, and a drain. The body cofntact is configured as an electrical contact of the body region. The body contact and the source overlap with each other to define an overlap region. The body contact has a depth from an upper surface of the semiconductor layer, wherein the depth is deeper than a depth of the source, whereby a part of the body contact is located vertically below the overlap region. A length of the overlap region in a channel direction is not shorter than a predetermined length, so as to suppress a parasitic bipolar junction transistor from being turning on when the high voltage device operates, wherein the parasitic bipolar junction transistor is formed by a part of the well, a part of the body region and a part of the source.
    Type: Application
    Filed: April 11, 2022
    Publication date: October 20, 2022
    Inventors: Chih-Wen Hsiung, Chun-Lung Chang, Kun-Huang Yu, Kuo-Chin Chiu, Wu-Te Weng
  • Patent number: 11460949
    Abstract: An electronic device, including a substrate, first electrodes, second electrodes, and peripheral wiring pairs, is provided. The substrate has a first peripheral area, a working area, and a second peripheral area arranged along a first direction. The first electrodes are disposed in the working area, structurally separated from each other, and arranged along a second direction. The second electrodes are disposed in the working area, structurally separated from each other, and arranged along the first direction. Each peripheral wiring pair includes first and second peripheral wirings respectively belonging to first and second conductive layers. One of the first and second peripheral wirings is disposed in one of the first and second peripheral areas. Other one of the first and second peripheral wirings is disposed in other one of the first and second peripheral areas. The first and second peripheral wirings are electrically connected to the same first electrode.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: October 4, 2022
    Assignee: Au Optronics Corporation
    Inventors: Chao-Kun Huang, Bo-Ru Jian, Kuo-Hsuan Huang
  • Patent number: 11459265
    Abstract: The disclosure relates to a Low Temperature Co-fired Ceramic (LTCC) substrate and a preparation method thereof, and in particular to a dielectric-constant-adjustable LTCC substrate and a preparation method thereof. The LTCC substrate of the disclosure includes the following components: glass, SiO2 and Al2O3, a weight percentage of the SiO2 in the LTCC substrate is 10% to 25%.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: October 4, 2022
    Assignee: GUANGDONG FENGHUA ADVANCED TECHNOLOGY HOLDING CO., LTD.
    Inventors: Tao Chen, Kun Huang, Shiwo Ta, Zhenxiao Fu, Yun Liu
  • Publication number: 20220274918
    Abstract: A biobased fatty acid arginate may be synthesized according to the disclosed process by combining arginine and a fatty acid. The fatty acid arginate may have certain beneficial properties, such as surfactant properties or acting as an antimicrobial agent.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Inventors: HELEN N. LEW, XUETONG FAN, KUN HUANG, JIANWEI ZHANG
  • Patent number: 11402316
    Abstract: Device and method for measuring two-phase relative permeability curve of unconventional oil reservoir are provided, wherein the device comprises: two-dimensional porous seepage microscopic model; injection components connected to inlet end of the two-dimensional porous seepage microscopic model; confining pressure components arranged outside the two-dimensional porous seepage microscopic model; a camera component arranged on one side of the two-dimensional porous seepage microscopic model; back pressure components connected to outlet end of the two-dimensional porous seepage microscopic model; and outlet pressure measuring and recovery components connected to outlet end of the two-dimensional porous seepage microscopic model. Two-phase relative permeability curve of unconventional oil reservoir can be measured accurately through the device.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: August 2, 2022
    Assignee: UNIVERSITY OF SCIENCE AND TECHNOLOGY BEIJING
    Inventors: Weiyao Zhu, Debin Kong, Qinglin Shu, Haien Yang, Kun Huang, Nan Li, Jing Xia
  • Publication number: 20220239224
    Abstract: A switching converter circuit for switching one end of an inductor therein between plural voltages according to a pulse width modulation (PWM) signal to convert an input voltage to an output voltage. The switching converter circuit has a driver circuit including a high side driver, a low side driver, a high side sensor circuit, and a low side sensor circuit. The high side sensor circuit is configured to sense a gate-source voltage of a high side metal oxide semiconductor field effect transistor (MOSFET), to generate a low side enable signal for enabling the low side driver to switch a low side MOSFET according to the PWM signal. The low side sensor circuit is configured to sense a gate-source voltage of a low side MOSFET, to generate a high side enable signal for enabling the high side driver to switch a high side MOSFET according to the PWM signal.
    Type: Application
    Filed: January 2, 2022
    Publication date: July 28, 2022
    Inventors: Ting-Wei Liao, Chien-Yu Chen, Kun-Huang Yu, Chien-Wei Chiu, Ta-Yung Yang
  • Publication number: 20220238727
    Abstract: The present invention provides a Zener diode and a manufacturing method thereof. The Zener diode includes: a semiconductor layer, an N-type region, and a P-type region. The N-type region has N-type conductivity, wherein the N-type region is formed in the semiconductor layer beneath an upper surface of the semiconductor layer, and in contact with the upper surface. The P-type region has P-type conductivity, wherein the P-type region is formed in the semiconductor layer and is completely beneath the N-type region, and in contact with the N-type region. The N-type region overlays the entire P-type region. The N-type region has an N-type conductivity dopant concentration, wherein the N-type conductivity dopant concentration is higher than a P-type conductivity dopant concentration of the P-type region.
    Type: Application
    Filed: January 7, 2022
    Publication date: July 28, 2022
    Inventors: Ting-Wei Liao, Chien-Yu Chen, Kun-Huang Yu, Wu-Te Weng, Chien-Wei Chiu, Ta-Yung Yang
  • Publication number: 20220239223
    Abstract: A switching converter circuit, which switches one terminal of an inductor to different voltages, includes a high side MOSFET, a low side MOSFET, and a driver circuit which includes a high side driver, a low side driver, and a dead time control circuit. According to an output current, The dead time control circuit adaptively delays a low side driving signal to generate a high side enable signal for enabling the high side driver to generate a high side driving signal according to a pulse width modulation (PWM) signal; and/or adaptively delays the high side driving signal to generate a low side enable signal for enabling the low side driver to generate the low side driving signal according to the PWM signal, so as to adaptively control a dead time in which the high side MOSFET and the low side MOSFET are both not conductive.
    Type: Application
    Filed: December 23, 2021
    Publication date: July 28, 2022
    Inventors: Ting-Wei Liao, Chien-Yu Chen, Kun-Huang Yu, Chien-Wei Chiu, Ta-Yung Yang
  • Patent number: 11396574
    Abstract: The disclosure relates to a self-healing omniphobic composition including a self-healing omniphobic polymer with a crosslinked backbone. The crosslinked backbone includes a reaction product between a polyisocyanate, a functionalized omniphobic polymer reactive therewith, a reversible polyfunctional linker including a hindered secondary amino group and/or an aromatic hydroxy group, and one or more polymeric backbone components. The crosslinked backbone includes reversible urea or reversible urethane bonds between the reversible polyfunctional linker and the polyisocyanate, which in turn provide self-healing properties to the omni-phobic composition. The self-healing omniphobic composition has favorable omniphobic properties, for example as characterized by water and/or oil contact and/or sliding angles. The omniphobic composition can be used as a coating on any of a variety of substrates to provide self-healing omniphobic properties to a surface of the substrate.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: July 26, 2022
    Assignee: BOARD OF TRUSTEES OF MICHIGAN STATE UNIVERSITY
    Inventors: Muhammad Rabnawaz, Ajmir Khan, Kun Huang
  • Publication number: 20220223464
    Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.
    Type: Application
    Filed: December 10, 2021
    Publication date: July 14, 2022
    Inventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Chih-Wen Hsiung, Chun-Lung Chang, Kuo-Chin Chiu, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
  • Publication number: 20220223733
    Abstract: A high voltage device includes: a semiconductor layer, a well region, a shallow trench isolation region, a drift oxide region, a body region, a gate, a source, and a drain. The drift oxide region is located on a drift region. The shallow trench isolation region is located below the drift oxide region. A part of the drift oxide region is located vertically above a part of the shallow trench isolation region and is in contact with the shallow trench isolation region. The shallow trench isolation region is formed between the drain and the body region.
    Type: Application
    Filed: December 10, 2021
    Publication date: July 14, 2022
    Inventors: Chun-Lung Chang, Chih-Wen Hsiung, Kun-Huang Yu, Kuo-Chin Chiu, Wu-Te Weng, Chien-Wei Chiu, Ta-Yung Yang
  • Publication number: 20220224325
    Abstract: A switch capable of decreasing parasitic inductance includes: a semiconductor device, a first top metal line, and a second top metal line. The second top metal line electrically connects a power supply input end and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged in parallel and adjacent to a second part of the second top metal line. When the semiconductor device is in an ON operation, an input current outflows from the power supply input end, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce an total parasitic inductance of the first top metal line and the second top metal line.
    Type: Application
    Filed: January 4, 2022
    Publication date: July 14, 2022
    Inventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
  • Publication number: 20220165880
    Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a gate, a source, a drain, and a drift oxide region. The semiconductor layer is formed on a substrate, wherein the semiconductor layer has at least one trench. The well is formed in the semicoducotor layer. The body region is formed in the well. The gate is formed on the well, and is in contact with the well. The source and the drain are located below, outside, and at different sides of the gate, in the body region and the well respectively. The drift oxide region is formed on a drift region, wherein a bottom surface of the drift oxide region is higher than a bottom surface of the trench.
    Type: Application
    Filed: February 7, 2022
    Publication date: May 26, 2022
    Inventors: Tsung-Yi Huang, Kun-Huang Yu, Ying-Shiou Lin, Chu-Feng Chen, Chung-Yu Hung, Yi-Rong Tu
  • Publication number: 20220157982
    Abstract: A high voltage device for use as an up-side switch of a power stage circuit includes: at least one lateral diffused metal oxide semiconductor (LDMOS) device, a second conductivity type isolation region and at least one Schottky barrier diode (SBD). The LDMOS device includes: a well formed in a semiconductor layer, a body region, a gate, a source and a drain. The second conductivity type isolation region is formed in the semiconductor layer and is electrically connected to the body region. The SBD includes: a Schottky metal layer formed on the semiconductor layer and a Schottky semiconductor layer formed in the semiconductor layer. The Schottky semiconductor layer and the Schottky metal layer form a Schottky contact. In the semiconductor layer, the Schottky semiconductor layer is adjacent to and in contact with the second conductivity type isolation region.
    Type: Application
    Filed: October 20, 2021
    Publication date: May 19, 2022
    Inventors: Kuo-Chin Chiu, Ta-Yung Yang, Chien-Wei Chiu, Wu-Te Weng, Chien-Yu Chen, Chih-Wen Hsiung, Chun-Lung Chang, Kun-Huang Yu, Ting-Wei Liao
  • Publication number: 20220147216
    Abstract: An electronic device, including a substrate, first electrodes, second electrodes, and peripheral wiring pairs, is provided. The substrate has a first peripheral area, a working area, and a second peripheral area arranged along a first direction. The first electrodes are disposed in the working area, structurally separated from each other, and arranged along a second direction. The second electrodes are disposed in the working area, structurally separated from each other, and arranged along the first direction. Each peripheral wiring pair includes first and second peripheral wirings respectively belonging to first and second conductive layers. One of the first and second peripheral wirings is disposed in one of the first and second peripheral areas. Other one of the first and second peripheral wirings is disposed in other one of the first and second peripheral areas. The first and second peripheral wirings are electrically connected to the same first electrode.
    Type: Application
    Filed: July 30, 2021
    Publication date: May 12, 2022
    Applicant: Au Optronics Corporation
    Inventors: Chao-Kun Huang, Bo-Ru Jian, Kuo-Hsuan Huang
  • Publication number: 20220114674
    Abstract: A computing system can implement a risk-assessment service through execution of a health lab data classifier model that classifies a prospective client's clinical health lab data, comprising a set of health aspect levels, within a set of health aspect ranges. When the set of health aspect levels of the prospective client are within a set of health aspect ranges, the computing system can generate one or more risk-mitigation packages at a particular tier of the risk-assessment service.
    Type: Application
    Filed: October 7, 2021
    Publication date: April 14, 2022
    Inventors: Ryan Hinchey, Munjal Shah, Gaurav Suri, Kun Huang, Kurt Roots, Bill Moore, Janel Obenchain
  • Publication number: 20220082487
    Abstract: Device and method for measuring two-phase relative permeability curve of unconventional oil reservoir are provided, wherein the device comprises: two-dimensional porous seepage microscopic model; injection components connected to inlet end of the two-dimensional porous seepage microscopic model; confining pressure components arranged outside the two-dimensional porous seepage microscopic model; a camera component arranged on one side of the two-dimensional porous seepage microscopic model; back pressure components connected to outlet end of the two-dimensional porous seepage microscopic model; and outlet pressure measuring and recovery components connected to outlet end of the two-dimensional porous seepage microscopic model. Two-phase relative permeability curve of unconventional oil reservoir can be measured accurately through the device.
    Type: Application
    Filed: November 22, 2021
    Publication date: March 17, 2022
    Inventors: WEIYAO ZHU, DEBIN KONG, QINGLIN SHU, HAIEN YANG, KUN HUANG, NAN LI, JING XIA
  • Publication number: 20220080360
    Abstract: This invention relates to a method of separating oils and aqueous media. The method uses membranes comprising 2D phyllosilicate coatings. The invention also relates to membranes for use in said methods.
    Type: Application
    Filed: January 20, 2020
    Publication date: March 17, 2022
    Inventors: Rahul Raveendran Nair, Kun Huang