Patents by Inventor Kun Zhang

Kun Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11948901
    Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a stack of layers. The stack of layers includes a common source layer, gate layers and insulating layers disposed on a substrate. The gate layers and insulating layers are stacked alternatingly. Then, the semiconductor device includes an array of channel structures formed in an array region. The channel structure extends through the stack of layers and forms a stack of transistors in a series configuration. The channel structure includes a channel layer that is in contact with the common source layer. The common source layer extends over the array region and a staircase region. The semiconductor device includes a contact structure disposed in the staircase region. The contact structure forms a conductive connection with the common source layer.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: April 2, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Kun Zhang
  • Publication number: 20240105266
    Abstract: A method for data erasing of a non-volatile memory device is disclosed. The memory includes multiple memory cell strings each including a select gate transistor and multiple memory cells that are connected in series. The method comprises applying a step erase voltage to one memory cell string for an erase operation, the step erase voltage having a step-rising shaped voltage waveform. The method further comprises, during a period when the step erase voltage rises from an intermediate level to a peak level, raising a voltage of the select gate transistor from a starting level to a peak level, and raising a voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in the one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.
    Type: Application
    Filed: September 22, 2022
    Publication date: March 28, 2024
    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Tao YANG, Dongxue ZHAO, Lei LIU, Kun ZHANG, Wenxi ZHOU, Zhiliang XIA, Zongliang HUO
  • Publication number: 20240097116
    Abstract: The invention discloses a ternary positive electrode material coated with nitride/graphitized carbon nanosheets and preparation method thereof. The ternary positive electrode material coated with nitride/graphitized carbon nanosheets includes a ternary positive electrode material matrix and a coating layer; the coating layer is composed of nitride and graphitized carbon; and the graphitized carbon is formed in situ in the coating process of the nitride. Compared with a physical mixing method, the in-situ generated carbon layer is connected to the material matrix more tightly, and the formed conductive network is denser. So that the rate performance of the material is improved to the maximum extent. The preparation method is simple and easy to realize industrial production. And the obtained ternary positive electrode material coated with nitride/graphitized carbon nanosheets has excellent rate performance and cycling stability.
    Type: Application
    Filed: October 26, 2023
    Publication date: March 21, 2024
    Inventors: Kaihua XU, Rui HE, Weifeng DING, Yunhe ZHANG, Xiang ZHANG, Kun ZHANG
  • Publication number: 20240098994
    Abstract: A three-dimensional (3D) memory device includes a stack structure including interleaved first conductive layers and first dielectric layers, and a channel structure extending through the stack structure along a first direction in contact with a first semiconductor layer at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The semiconductor channel includes an angled structure, and a first width of the semiconductor channel at the bottom portion of the channel structure below the angled structure is smaller than a second width of the semiconductor channel at an upper portion of the channel structure above the angled structure.
    Type: Application
    Filed: November 9, 2022
    Publication date: March 21, 2024
    Inventors: Linchun Wu, Shuangshuang Wu, Lei Li, Kun Zhang, Zhiliang Xia, Zongliang Huo
  • Patent number: 11934449
    Abstract: Provided are a method and apparatus for processing map information, a device, and a storage medium which relate to the field of computer technology and, in particular, to the fields of intelligent transportation and computer vision technology. The specific implementation includes that an object in an image for query is recognized to obtain an object recognition result and that a target point of interest matching the image for query is selected from at least one candidate point of interest of an electronic map according to the object recognition result.
    Type: Grant
    Filed: September 9, 2022
    Date of Patent: March 19, 2024
    Assignee: Beijing Baidu Netcom Science Technology Co., Ltd.
    Inventors: Jia Zhao, Meng Xu, Kun Zhang
  • Patent number: 11935596
    Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit of the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: March 19, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Yanhong Wang, Wei Liu, Liang Chen, Zhiliang Xia, Wenxi Zhou, Kun Zhang, Yuancheng Yang
  • Patent number: 11934832
    Abstract: This application discloses example synchronization instruction insertion methods and example apparatuses. One example method includes obtaining a first program block comprising one or more statements, where each of the one or more statements includes one or more function instructions. A first function instruction and a second function instruction between which data dependency exists in the first program block can then be determined. A synchronization instruction pair between a first statement including the first function instruction and a second statement including the second function instruction can then be inserted.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: March 19, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xiong Gao, Kun Zhang
  • Patent number: 11932238
    Abstract: The disclosed technology enables automated parking of an autonomous vehicle. An example method of performing automated parking for a vehicle comprises obtaining, from a plurality of global positioning system (GPS) devices located on or in an autonomous vehicle, a first set of location information that describes locations of multiple points on the autonomous vehicle, where the first set of location information are associated with a first position of the autonomous vehicle, determining, based on the first set of location information and a location of the parking area, a trajectory information that describes a trajectory for the autonomous vehicle to be driven from the first position of the autonomous vehicle to a parking area, and causing the autonomous vehicle to be driven along the trajectory to the parking area by causing operation of one or more devices located in the autonomous vehicle based on at least the trajectory information.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: March 19, 2024
    Assignee: TUSIMPLE, INC.
    Inventors: Kun Zhang, Xiaoling Han, Zehua Huang, Charles A. Price
  • Patent number: 11935634
    Abstract: A system for predicting and summarizing medical events from electronic health records includes a computer memory storing aggregated electronic health records from a multitude of patients of diverse age, health conditions, and demographics including medications, laboratory values, diagnoses, vital signs, and medical notes. The aggregated electronic health records are converted into a single standardized data structure format and ordered arrangement per patient, e.g., into a chronological order. A computer (or computer system) executes one or more deep learning models trained on the aggregated health records to predict one or more future clinical events and summarize pertinent past medical events related to the predicted events on an input electronic health record of a patient having the standardized data structure format and ordered into a chronological order.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: March 19, 2024
    Assignee: Google LLC
    Inventors: Alexander Mossin, Alvin Rajkomar, Eyal Oren, James Wilson, James Wexler, Patrik Sundberg, Andrew Dai, Yingwei Cui, Gregory Corrado, Hector Yee, Jacob Marcus, Jeffrey Dean, Benjamin Irvine, Kai Chen, Kun Zhang, Michaela Hardt, Xiaomi Sun, Nissan Hajaj, Peter Junteng Liu, Quoc Le, Xiaobing Liu, Yi Zhang
  • Patent number: 11935862
    Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a first semiconductor structure, a second semiconductor structure opposite to the first semiconductor structure, and an interface layer between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The second semiconductor structure includes a plurality of peripheral circuits electrically connected to the memory stack. The interface layer includes single crystalline silicon and a plurality of interconnects between the memory stack and the peripheral circuits.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: March 19, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Kun Zhang
  • Publication number: 20240086110
    Abstract: A data storage method includes: in response to a stream ID carried by an IO write request of a host satisfying a first preset condition, writing data corresponding to the IO write request into a first storage unit; and in response to the stream ID carried by the IO write request satisfying a second preset condition, writing the data corresponding to the IO write request into a second storage unit, wherein the stream ID indicates write latency requirement information of the data corresponding to the IO write request, wherein a data write latency indicated by the stream ID satisfying the first preset condition is less than the data write latency indicated by the stream ID satisfying the second preset condition, wherein a read and write performance of the first storage unit is higher than the read and write performance of the second storage unit.
    Type: Application
    Filed: March 21, 2023
    Publication date: March 14, 2024
    Inventors: Bei QI, Kun Zhang, Kun Dou, Ruyi Zhang, Zongyuan Zhang, Yutao Li, Dan Cao, Tianyi Zhang
  • Patent number: 11929119
    Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, and a first bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells. The second semiconductor structure includes a first peripheral circuit of the array of memory cells. The first peripheral circuit includes a first transistor. A third semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The first semiconductor structure, the second semiconductor structure, and the third semiconductor structure are stacked over one another.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: March 12, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Liang Chen, Wei Liu, Yanhong Wang, Zhiliang Xia, Wenxi Zhou, Kun Zhang, Yuancheng Yang
  • Patent number: 11927563
    Abstract: A smart acoustic information recognition-based welded weld impact quality determination method and system, comprising: controlling a tip of an ultrasonic impact gun (1) to perform impact treatment on a welded weld with different treatment pressures, treatment speeds, treatment angles and impact frequencies, obtaining acoustic signals during the impact treatment, calculating feature values of the acoustic signals, and constructing an acoustic signal sample set including various stress conditions; marking the acoustic signal sample set according to impact treatment quality assessment results for the welded weld; establishing a multi-weight neural network model, and using the marked acoustic signal sample set to train the multi-weight neural network model; obtaining feature values of welded weld impact treatment acoustic signals to be determined, inputting the feature values into the trained multi-weight neural network model, and outputting determination results for welded weld impact treatment quality to be det
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: March 12, 2024
    Assignee: NANTONG UNIVERSITY
    Inventors: Liang Hua, Ling Jiang, Juping Gu, Cheng Lu, Kun Zhang, Kecai Cao, Liangliang Shang, Qi Zhang, Shenfeng Wang, Yuxuan Ge, Zixi Ling, Jiawei Miao
  • Publication number: 20240076712
    Abstract: Compositions and methods are provided for simple, instrument-free and sensitive methods that enable rapid, point-of-care detection of nucleic acid molecules of interest. This is based on a surprising discovery that the relative efficiencies of amplification and CRISPR-based cleavage and detection can be tuned to favor amplification until sufficient amplified products are generated to enable detection. Example approaches include design of guide RNA and primers to target nonoptimal PAM sequences, or sequence-engineering Cas nucleases to reduce activities informing a ribonucleoprotein with the guide RNA or binding to or cleaving the substrate nucleic acid.
    Type: Application
    Filed: January 7, 2022
    Publication date: March 7, 2024
    Inventors: Hao Yin, Shuhan Lu, Ying Zhang, Xiaohan Tong, Kun Zhang, Xi Zhou, Dingyu Zhang
  • Publication number: 20240074181
    Abstract: A memory device includes a stack structure, channel structures, and a slit structure. The stack structure includes interleaved conductive layers and dielectric layers, and the conductive layers include a plurality of word lines. Each of the channel structures extends vertically through the stack structure. The slit structure extends vertically through the stack structure. An outer region of the stack structure includes a staircase structure, and the interleaved conductive layers and dielectric layers in a bottom portion of the stack structure are wider than the interleaved conductive layers and dielectric layers in a top portion of the stack structure. A first outer width of the slit structure in the bottom portion of the stack structure is greater than a second outer width of the slit structure in the top portion of the stack structure.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Inventors: Linchun Wu, Kun Zhang, Wenxi Zhou, Cuicui Kong, Shuangshuang Wu, Zhiliang Xia, Zongliang Huo
  • Patent number: 11913017
    Abstract: A guide RNA comprising: a gRNA spacer sequence at the 5? end of the guide RNA, wherein the spacer sequence is complementary to a target gene, a scaffold sequence that binds to Cas9, and an RNA capture and sequencing domain comprising: a barcode sequence, and a primer binding sequence; nucleic acids and vectors encoding the guide RNA; cells expressing the guide RNA; and a library comprising a plurality of guide RNAs. Also disclosed are methods of introducing a genetic perturbation into a cell, methods of assessing an effect of at least one genetic perturbation on RNA expression in a cell, methods of identifying nucleic acid sequences associated with a disease state and a method of identifying candidate therapeutic agents.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: February 27, 2024
    Assignee: The Regents of the University of California
    Inventors: Kun Zhang, Prashant Mali, Yan Wu, Dongxin Zhao
  • Patent number: 11912986
    Abstract: Understanding the complex effects of genetic perturbations on cellular state and fitness in human pluripotent stem cells (hPSCs) has been challenging using traditional pooled screening techniques which typically rely on unidimensional phenotypic readouts. Here, Applicants use barcoded open reading frame (ORF) overexpression libraries with a coupled single-cell RNA sequencing (scRNA-seq) and fitness screening approach, a technique we call SEUSS (ScalablE fUnctional Screening by Sequencing), to establish a comprehensive assaying platform. Using this system, Applicants perturbed hPSCs with a library of developmentally critical transcription factors (TFs), and assayed the impact of TF overexpression on fitness and transcriptomic cell state across multiple media conditions. Applicants further leveraged the versatility of the ORF library approach to systematically assay mutant gene libraries and also whole gene families.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: February 27, 2024
    Assignee: The Regents of the University of California
    Inventors: Prashant Mali, Udit Parekh, Yan Wu, Kun Zhang
  • Publication number: 20240063455
    Abstract: The present invention provides a method for recovering valuable metals from waste lithium ion batteries. The method comprises: short-circuit discharging, dismantling, crushing, roasting, and screening on waste lithium ion batteries to obtain active electrode powders; using alkaline solution to wash the active electrode powders, then filtering to remove copper and aluminum; drying the activated electrode powder after alkaline washing treatment, mix the dried activated electrode powder with starch and concentrated sulfuric acid and stir evenly to obtain the mixed material; calcining the mixed material with controlling the atmosphere; taking out the product obtained from calcination and using deionized water to extract the leachate and leaching residue with valence metal ions, and then obtaining the leachate after filtering.
    Type: Application
    Filed: October 31, 2023
    Publication date: February 22, 2024
    Inventors: Kaihua XU, Liangxing JIANG, Jian YANG, Kun ZHANG, Chenwei LI, Yongan CHEN, Yanqing LAI
  • Publication number: 20240064978
    Abstract: A three-dimensional (3D) memory device includes a stack, a plurality of contact structures, and a plurality of support structures. The stack in an insulating structure includes a plurality of conductive layers and a plurality of dielectric layers stacked alternatingly, and the stack includes a staircase structure. The plurality of contact structures each extends through the insulating structure and in contact with a respective conductive layer of the plurality of conductive layers in the staircase structure. The plurality of support structures extends through the stack in the staircase structure. Each support structure is in contact with one of the plurality of contact structures.
    Type: Application
    Filed: August 18, 2022
    Publication date: February 22, 2024
    Inventors: Jingtao Xie, Bingjie Yan, Kun Zhang, Wenxi Zhou, Zhiliang Xia, Zongliang Huo
  • Publication number: 20240063140
    Abstract: A three-dimensional (3D) memory device includes a stack, a plurality of contact structures, and a plurality of support structures. The stack in an insulating structure includes conductive layers and dielectric layers stacked alternatingly, and the stack includes a staircase structure. Each contact structure extends through the insulating structure and is in contact with a respective conductive layer in the staircase structure. The support structures extend through the stack in the staircase structure. The contact structures are arranged in a first row and a second row, the first row of contact structures is in electrical contact with the peripheral device, and the second row of contact structures is in electrical insulation with the peripheral device.
    Type: Application
    Filed: August 18, 2022
    Publication date: February 22, 2024
    Inventors: Jingtao Xie, Bingjie Yan, Kun Zhang, Wenxi Zhou, Zhiliang Xia, Zongliang Huo