Abstract: A low-voltage user demand response interaction apparatus and an operation method therefor. The apparatus comprises an electrical loop, a mechanical switch, a protection module, a data collection module, a control processor, a power supply module, a communication module, a load identification module, a blockchain module and a demand response module, wherein the mechanical switch is connected to the electrical loop; the protection module is connected to the mechanical switch; the control processor is connected to the protection module; the load identification module, the blockchain module and the demand response module are respectively connected to the control processor; the data collection module is connected to the electrical loop, and transmits data to the control processor; and the communication module and the power supply module are respectively connected to the control processor.

Abstract: The invention discloses a ternary positive electrode material coated with nitride/graphitized carbon nanosheets and preparation method thereof. The ternary positive electrode material coated with nitride/graphitized carbon nanosheets includes a ternary positive electrode material matrix and a coating layer; the coating layer is composed of nitride and graphitized carbon; and the graphitized carbon is formed in situ in the coating process of the nitride. Compared with a physical mixing method, the in-situ generated carbon layer is connected to the material matrix more tightly, and the formed conductive network is denser. So that the rate performance of the material is improved to the maximum extent. The preparation method is simple and easy to realize industrial production. And the obtained ternary positive electrode material coated with nitride/graphitized carbon nanosheets has excellent rate performance and cycling stability.

Abstract: This disclosure is directed to methods for performing operations on a memory device. The memory device can include a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar and a bit line formed above the drain cap. The method can include applying a first positive voltage bias to the bottom select gate and applying a second positive voltage bias to the word line. The method can also include applying a third positive voltage bias to the bit line after the word line reaches the second positive voltage bias. The method can further include applying a ground voltage to the word line and applying the ground voltage to the bit line.

Abstract: A rapid detection tool for a coaxial relationship based on a photosensitive material and a detection method using the same are used to detect coaxiality of two through-holes in the same workpiece to be detected. An image processing unit and a control unit are mounted outside a light-shielding box. Light sources, cameras, sensors, and an air cylinder are mounted in the light-shielding box. A photosensitive plate coated with a photosensitive resin is placed between the two holes, and two sides are irradiated by the light sources. Coordinates of centers of circular patterns formed on the photosensitive plate are calculated so that a coaxial relationship between the two holes can be accurately obtained. An output rod of the air cylinder is controlled to extend outward to reject a workpiece to be detected not meeting requirements.

Abstract: Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The third semiconductor structure and the fourth semiconductor structure are sandwiched between the first semiconductor structure and the second semiconductor structure in a vertical direction.

Abstract: Three-dimensional (3D) memory devices and fabricating methods are disclose. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The first semiconductor structure and the second semiconductor structure are sandwiched between the third semiconductor structure and the fourth semiconductor structure in a vertical direction.

Abstract: Three-dimensional (3D) memory devices and fabricating methods are disclose. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The first semiconductor structure, the second semiconductor structure, the third semiconductor structure, and the fourth semiconductor structure are stacked over one another.

Abstract: A memory device includes an array of memory cells disposed on a first side of a first semiconductor layer, and a pad-out structure disposed on the array of memory cells. Each of the memory cells includes a semiconductor body extending in a first direction, a first terminal in contact with the first side of the first semiconductor layer and a second terminal are formed at both ends of the semiconductor body; a word line extending in a second direction perpendicular to the first direction; and a plate line extending in the second direction.

Abstract: A memory device includes an array of memory cells disposed on a first side of a first semiconductor layer, and a peripheral circuit bonded to the array of memory cells. Each of the memory cells includes a semiconductor body extending in a first direction, a first terminal and a second terminal are formed at both ends of the semiconductor body; a word line extending in a second direction perpendicular to the first direction; plate lines extending in the second direction; and a first dielectric layer disposed between the semiconductor body and the word line and the plate line.

Abstract: A three-dimensional (3D) memory device includes a memory array device, a peripheral device, an etch stop layer, and a backside gate line slit. The memory array device includes a frontside and a backside, a plurality of memory strings, and a plurality of word lines in a staircase structure coupled to the plurality of memory strings. The peripheral device is above the frontside of the memory array device. The etch stop layer is between the memory array device and the peripheral device. The backside gate line slit extends through the backside of the memory array device to the etch stop layer. The backside gate line slit includes a conductive gate line layer and an insulating gate line layer. The 3D memory device can increase manufacturing efficiency, increase yield, reduce thermal stress, reduce fluorine contamination, increase an overlay window, and decrease overlay errors.

Abstract: Three-dimensional (3D) memory devices and fabricating methods are disclose. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The third semiconductor structure is sandwiched between the first semiconductor structure and the fourth semiconductor structure, and the fourth semiconductor is sandwiched between the second semiconductor structure and the third semiconductor structure.

Abstract: A method for forming a 3D memory device is disclosed. A channel structure extending vertically through a dielectric stack including interleaved sacrificial layers and dielectric layers above a substrate is formed. A sacrificial plug above and in contact with the channel structure is formed. A slit opening extending vertically through the dielectric stack is formed. A memory stack including interleaved conductive layers and the dielectric layers is formed by replacing, through the slit opening, the sacrificial layers with the conductive layers. A first contact portion is formed in the slit opening. The sacrificial plug is removed after forming the first contact portion to expose the channel structure. A channel local contact above and in contact with the channel structure, and a second contact portion above the first contact portion in the slit opening are simultaneously formed.

Abstract: A memory device includes a first semiconductor layer, a first memory array, a second memory array, and a first peripheral circuit. The first memory array is disposed on a first side of the first semiconductor layer. The first memory array includes first memory cells, and first split structures. The second memory array is disposed on a second side of the first semiconductor layer opposite to the first side. The second memory array includes second memory cells, and second split structures. The first peripheral circuit including a first peripheral device disposed on the first memory array.

Abstract: A memory device includes a semiconductor layer; a peripheral circuit disposed on the semiconductor layer; and an array of memory cells disposed aside the peripheral circuit on the semiconductor layer. Each of the memory cells includes a semiconductor body extending in a first direction, a first end of the semiconductor body is in contact with the semiconductor layer; a word line gate extending in a second direction perpendicular to the first direction; a plate line gate extending in the second direction; and a dielectric layer disposed between the semiconductor body and the word line gate and the plate line gate.

Abstract: A method, an apparatus, a device, and a storage medium for issuing and replying to multimedia content are provided here. The method described herein for issuing multimedia content comprises: receiving push content associated with a user, the push content being generated based on an the occurrence of a personalized event associated with the user; presenting the push content to the user, the push content comprising video content related to the personalized event; and issuing multimedia content associated with the personalized event based on an operation on the push content by the user, the multimedia content being generated based on the push content. According to the embodiments of the present disclosure, it can effectively help a user to create multimedia content associated with a personalized event, reduce the time cost for the user, and can effectively guide interaction between users, thereby improving user experience.

Abstract: The disclosed technology enables automated parking of an autonomous vehicle. An example method of performing automated parking for a vehicle comprises obtaining, from a plurality of global positioning system (GPS) devices located on or in an autonomous vehicle, a first set of location information that describes locations of multiple points on the autonomous vehicle, where the first set of location information are associated with a first position of the autonomous vehicle, determining, based on the first set of location information and a location of the parking area, a trajectory information that describes a trajectory for the autonomous vehicle to be driven from the first position of the autonomous vehicle to a parking area, and causing the autonomous vehicle to be driven along the trajectory to the parking area by causing operation of one or more devices located in the autonomous vehicle based on at least the trajectory information.

Abstract: A log-structured merge-tree (LSM-Tree) based key-value (KV) data storage method includes writing KV data into a NAND flash memory. The KV data includes a key-value pair including a key and a corresponding value. The KV data is stored in a key-value solid state drive (KVSSD), which includes a storage class memory (SCM) and the NAND flash memory. The method further includes storing metadata of the KV data in the SCM. The metadata of the KV data includes the key and index information of the corresponding value of the KV data, and the index information of the corresponding value of the KV data indicates address information of the KV data in the NAND flash memory.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a plurality of memory blocks in a plan view and at least one stabilization structure extending laterally to separate adjacent ones of the memory blocks in the plan view. Each of the memory blocks includes a memory stack including vertically interleaved conductive layers and first dielectric layers, and a plurality of channel structures each extending vertically through the memory stack. The stabilization structure includes a dielectric stack including vertically interleaved second dielectric layers and the first dielectric layers.