Patents by Inventor LIANG YI

LIANG YI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing semiconductor device for reducing grain size of polysilicon
    Patent number: 9852912
    Abstract: A method of manufacturing a semiconductor device includes providing a silicon substrate with multiple layers formed on a front side and a backside, wherein at least a dielectric layer is formed on the backside of the silicon substrate; defining isolation regions and active regions at the front side of the silicon substrate, wherein the active regions are separated by the isolation regions; treating the multiple layers formed at the front side and the backside of the silicon substrate, so as to remain the dielectric layer as an outermost layer exposed at the backside of the silicon substrate; and depositing a polysilicon layer on the isolation regions and the active regions at the front side of the silicon substrate.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: December 26, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng Zhang, Liang Yi, Wen-Bo Ding, Chien-Kee Pang, Yu-Yang Chen
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20170317205
    Abstract: A method for manufacturing a semiconductor device is provided, including forming a plurality of fins on a semiconductor substrate, and forming source/drain regions on the fins. The source/drain regions have an uneven surface with a mean surface roughness, Ra, of about 10 nm to about 50 nm. A smoothing layer is formed on the source/drain regions filling the uneven surface. An etch stop layer is formed overlying the smoothing layer. A portion of the etch stop layer is removed to expose a portion of the smoothing layer. The exposed smoothing layer is removed, and a contact layer is formed on the source/drain regions.
    Type: Application
    Filed: May 9, 2017
    Publication date: November 2, 2017
    Inventors: Chen-Ming LEE, Liang-Yi CHEN, Fu-Kai YANG, Mei-Yun WANG
  • Resistive random access memory and method of forming the same
    Patent number: 9806255
    Abstract: A resistive random access memory includes a lower electrode, an upper electrode and a resistive layer between the lower electrode and the upper electrode, wherein the resistive layer includes a constant-resistance portion and a variable-resistance portion surrounding the constant-resistance portion.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: October 31, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ching Hsu, Liang Yi, Shen-De Wang, Ko-Chi Chen
  • Semiconductor device and method of making the same
    Patent number: 9799705
    Abstract: The present invention provides a semiconductor device. The semiconductor device includes a contact structure disposed in a first dielectric layer, a second dielectric layer disposed on the first dielectric layer and having an opening disposed therein, a spacer disposed in the opening and partially covering the contact structure, and a resistive random-access memory (RRAM) disposed on the contact structure and directly contacting the spacer, wherein the RRAM includes a bottom electrode, a top electrode, and a switching resistance layer disposed between the bottom electrode and the top electrode.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: October 24, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Liang Yi, Chia-Ching Hsu, Shen-De Wang, Ko-Chi Chen, Guoan Du
  • Silicon germanium p-channel FinFET stressor structure and method of making same
    Patent number: 9793404
    Abstract: A source/drain (S/D) structure includes a SiGe structure epitaxially grown and having sloped facets on a recessed fin structure disposed adjacent to a channel portion of a finFET, a first Ge structure having a rounded surface epitaxially grown on the SiGe structure, and a capping layer formed over the rounded surface of the Ge structure. The capping layer may be formed of Si. Such S/D structures provide both a larger physical size for lower contact resistance, and greater volume and concentration of Ge for higher compressive strain applied to the channel portion of the finFET.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: October 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Chang Sung, Liang-Yi Chen
  • STATOR, SINGLE PHASE MOTOR AND FAN
    Publication number: 20170279342
    Abstract: A stator includes a stator core including stator poles and a yoke connecting the stator poles, at least one winding wound around the stator core and connecting terminals configured to connect with an external power source to supply power to the winding and located at one end of the yoke adjacent the stator poles. A single phase motor and a ventilation fan are also provided.
    Type: Application
    Filed: March 28, 2017
    Publication date: September 28, 2017
    Inventors: Min LI, Kok Ang CHONG, Xiao Lin ZHANG, Hai Yang WANG, Moola Mallikarjuna REDDY, Yue LI, Chui You ZHOU, Hong Liang YI, Yong Gang ZHANG, Yong WANG
  • ELECTRIC MOTOR AND ELECTRIC APPARATUS USING SAME
    Publication number: 20170271968
    Abstract: An electric motor includes a stator and a rotor rotatably mounted to the stator. The rotor includes a rotary shaft; a rotor main body attached around the rotary shaft, the rotor main body and the rotary shaft being loosely fit with each other thus allowing for a rotation speed difference therebetween; and a buffering device arranged between the rotor main body and the rotary shaft for synchronizing rotation speeds of the rotor main body and the rotary shaft in a time-delayed manner. The motor is preferably a single phase synchronous motor. An electrical apparatus using the motor is also provided.
    Type: Application
    Filed: March 15, 2017
    Publication date: September 21, 2017
    Inventors: Yue LI, Chui You ZHOU, Xiao Ning ZHU, Yong WANG, Yong Gang ZHANG, Hong Liang YI, Ya Ming ZHANG
  • ELECTRIC MOTOR AND FAN ASSEMBLY USING THE SAME
    Publication number: 20170271946
    Abstract: An electric motor includes a stator and a rotor rotatably mounted to the stator. The rotor includes a rotary shaft, a rotor main body attached around the rotary shaft, the rotor main body being rotatable under the interaction between the rotor main body and the stator when the winding is energized. The rotor main body and the rotary shaft are in a loose fitting with each other to allow a rotation speed difference being existed between the rotor main body and the rotary shaft during startup of the rotor. A time-delayed synchronization mechanism is connected between the rotary shaft and the rotor main body and configured to eliminate, with time delay, the rotation speed difference between the rotor main body and the rotary shaft.
    Type: Application
    Filed: March 15, 2017
    Publication date: September 21, 2017
    Inventors: Yue LI, Chui You ZHOU, Yong WANG, Wei ZHANG, Xiao Ning ZHU, Hong Liang YI, Yong Gang ZHANG, Ya Ming ZHANG
  • Touch panel
    Patent number: 9733771
    Abstract: A touch panel includes a plurality of first axial electrodes, a plurality of second axial electrodes and trace region. The first axial electrodes extend along a first axial direction. The second axial electrodes extend along the first axial direction and disposed to insulatively correspond to the first axial electrodes. Each of the second axial electrodes includes a central electrode, and a plurality of first branch electrodes which are electrically coupled to the central electrode, and have areas different from one another. Each of the first branch electrodes overlaps a corresponding one of the first axial electrodes. The trace region is disposed at one side of the first and second axial electrodes along the first axial direction.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: August 15, 2017
    Assignee: TPK Touch Systems (XIAMEN) Inc
    Inventors: Meifang Lan, Pudi Hong, Yiyun Lai, Liang-Yi Chang
  • FLASH MEMORY AND METHOD OF FABRICATING THE SAME
    Publication number: 20170221911
    Abstract: The flash memory includes a stacked gate disposed on a substrate. The stacked gate includes an erase gate and two floating gates. Each floating gate has an acute angle pointing toward the erase gate. There is a high electric field formed around the acute angle so that the flash memory can perform an erase mode even at a lower operational voltage. Furthermore, the flash memory does not use any control gate to perform a write mode.
    Type: Application
    Filed: March 28, 2016
    Publication date: August 3, 2017
    Inventors: Liang Yi, Ko-Chi Chen, Shen-De Wang
  • METHOD OF PREPARING SELECTIVE CATALYTIC REDUCTION COMPOSITE CATALYST
    Publication number: 20170173567
    Abstract: A method of preparing selective catalytic reduction composite catalyst is provided. First, first metal compound support, second metal compound, third metal compound and water are mixed to formed a precursor solution. Then, dried mixture powder is formed from the precursor solution by a spray-drying process. Thereafter, a calcination process is performed on the dried mixture powder.
    Type: Application
    Filed: March 14, 2016
    Publication date: June 22, 2017
    Inventors: Hsun-Ling Bai, Liang-Yi Lin, Tsung-Yu Lee, You-Ren Zhang
  • Semiconductor device and manufacturing method thereof
    Patent number: 9685439
    Abstract: A method for manufacturing a semiconductor device is provided, including forming a plurality of fins on a semiconductor substrate, and forming source/drain regions on the fins. The source/drain regions have an uneven surface with a mean surface roughness, Ra, of about 10 nm to about 50 nm. A smoothing layer is formed on the source/drain regions filling the uneven surface. An etch stop layer is formed overlying the smoothing layer. A portion of the etch stop layer is removed to expose a portion of the smoothing layer. The exposed smoothing layer is removed, and a contact layer is formed on the source/drain regions.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: June 20, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Ming Lee, Liang-Yi Chen, Fu-Kai Yang, Mei-Yun Wang
  • Silicon Germanium P-Channel FinFET Stressor Structure and Method of Making Same
    Publication number: 20170154990
    Abstract: A source/drain (S/D) structure includes a SiGe structure epitaxially grown and having sloped facets on a recessed fin structure disposed adjacent to a channel portion of a finFET, a first Ge structure having a rounded surface epitaxially grown on the SiGe structure, and a capping layer formed over the rounded surface of the Ge structure. The capping layer may be formed of Si. Such S/D structures provide both a larger physical size for lower contact resistance, and greater volume and concentration of Ge for higher compressive strain applied to the channel portion of the finFET.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 1, 2017
    Inventors: Hsueh-Chang Sung, Liang-Yi CHEN
  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20170110469
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, a non-volatile memory cell, and a gate stack. The non-volatile memory cell is formed in the semiconductor substrate, and a top surface of the non-volatile memory cell is coplanar with or below a top surface of the semiconductor substrate. The gate stack is formed on the semiconductor substrate.
    Type: Application
    Filed: November 24, 2015
    Publication date: April 20, 2017
    Inventors: Liang Yi, Ko-Chi Chen, Shen-De Wang
  • Voltage regulation circuit
    Patent number: 9625933
    Abstract: A switchable voltage regulation circuit includes a power supply chip and a voltage regulation module. The voltage regulation module includes first and second resistors and first and second switch units. A first terminal of the first resistor is electrically coupled to a power supply and a first output pin of the power supply chip. A first terminal of the second resistor is electrically coupled to the second terminal of the first resistor. The first switch unit is electrically coupled between the first terminal of the first resistor and the second terminal of the first resistor. The second switch unit is electrically coupled between the first terminal of the second resistor and the voltage output. By manual switching, or by transistors under control of a baseboard management unit, the resistances can be switched in or switched out to regulate the voltage.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: April 18, 2017
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Liang-Yi Cui, Jun-Jun Lu
  • VOLTAGE REGULATION CIRCUIT
    Publication number: 20170090502
    Abstract: A switchable voltage regulation circuit includes a power supply chip and a voltage regulation module. The voltage regulation module includes first and second resistors and first and second switch units. A first terminal of the first resistor is electrically coupled to a power supply and a first output pin of the power supply chip. A first terminal of the second resistor is electrically coupled to the second terminal of the first resistor. The first switch unit is electrically coupled between the first terminal of the first resistor and the second terminal of the first resistor. The second switch unit is electrically coupled between the first terminal of the second resistor and the voltage output. By manual switching, or by transistors under control of a baseboard management unit, the resistances can be switched in or switched out to regulate the voltage.
    Type: Application
    Filed: October 23, 2015
    Publication date: March 30, 2017
    Inventors: LIANG-YI CUI, JUN-JUN LU
  • Oxide Electron Selective Layers
    Publication number: 20170092697
    Abstract: Oxide electron selective contacts for perovskite solar cells are provided. In one aspect, a method of forming a perovskite solar cell is provided. The method includes the steps of: depositing a layer of a hole transporting material on a substrate; forming a perovskite absorber on the hole transporting material; depositing an oxide electron transporting material on the perovskite absorber; and forming a top electrode on the oxide electron transporting material. Perovskite solar cells and tandem photovoltaic devices are also provided.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: Liang-yi Chang, Supratik Guha, Teodor K. Todorov
  • Electronic device having a thermal conductor made of silver between a heat sink and an electronic element, and fabrication method thereof
    Patent number: 9607923
    Abstract: An electronic device is provided, which includes an electronic element and a heat dissipating element disposed on the electronic element through a thermal conductor, wherein a width of the thermal conductor is smaller than a width of the electronic element. The thermal conductor includes silver to thereby greatly increase the thermal conductivity of the thermal conductor and hence improve the thermal conduction efficiency of the electronic device.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: March 28, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chung-Jen Hung, Chi-An Pan, Chi-Hsiang Hsu, Liang-Yi Hung
  • Hybrid Vapor Phase-Solution Phase Growth Techniques for Improved CZT(S,Se) Photovoltaic Device Performance
    Publication number: 20170077338
    Abstract: A hybrid vapor phase-solution phase CZT(S,Se) growth technique is provided. In one aspect, a method of forming a kesterite absorber material on a substrate includes the steps of: depositing a layer of a first kesterite material on the substrate using a vapor phase deposition process, wherein the first kesterite material includes Cu, Zn, Sn, and at least one of S and Se; annealing the first kesterite material to crystallize the first kesterite material; and depositing a layer of a second kesterite material on a side of the first kesterite material opposite the substrate using a solution phase deposition process, wherein the second kesterite material includes Cu, Zn, Sn, and at least one of S and Se, wherein the first kesterite material and the second kesterite material form a multi-layer stack of the absorber material on the substrate. A photovoltaic device and method of formation thereof are also provided.
    Type: Application
    Filed: November 3, 2016
    Publication date: March 16, 2017
    Inventors: Liang-Yi Chang, Talia S. Gershon, Richard A. Haight, Yun Seog Lee
  • Single Phase Motor And Electrical Device Using Same
    Publication number: 20170063176
    Abstract: A single phase motor and an electrical device are provided. The single phase motor includes a stator and a rotor. The stator includes a stator core and a winding wound around the stator core. The stator core includes a yoke and two opposed pole portions. Each pole portion includes short and long pole shoes. The rotor is received in a space defined by the short and long pole shoes of the two pole portions. The short pole shoe of each pole portion and the long pole shoe of the opposite pole portion are located adjacent to each other and define a slot opening therebetween. Each pole portion includes the short pole shoe and long pole shoe, which provides the motor with different startup capabilities along the clockwise and counter-clockwise directions.
    Type: Application
    Filed: September 1, 2016
    Publication date: March 2, 2017
    Inventors: Yue LI, Chui You ZHOU, Hong Liang Yi, Yong Gang ZHANG, Yong WANG, Wei ZHANG, Xiao Ning ZHU, Yong LI