Abstract: A serial-parallel conversion circuit for converting a high-speed serial signal to a parallel signal is provided. Further, a display device with high image quality and fewer external connection terminals is provided. Furthermore, a method for driving a serial-parallel conversion circuit for converting a high-speed serial signal to a parallel signal is provided. A serial-parallel conversion circuit includes a plurality of units in each of which a sampling switch and an amplifier are connected to each other. In the serial-parallel conversion circuit, each sampling switch is configured to output part of a serial signal to its respective amplifier only through one transistor.

Abstract: When a CPU provided with a latch memory is operated, a constant storage method or an end storage method is selected depending on what is processed by the CPU; thus, the CPU provided with a latch memory has low power consumption. When the CPU provided with a latch memory is operated, in the case where the number of times of turning on and off the power source is high, a constant storage method is employed and in the case where the number of times of turning on and off the power source is low, an end storage method is employed. Whether a constant storage method or an end storage method is selected is determined based on the threshold value set depending on power consumption.

Abstract: An object is to provide a rectifier circuit of which the drop in the output voltage by the threshold voltage of a transistor used as a rectifier element is suppressed. Another object is to provide a rectifier circuit whose variations in the output voltage are suppressed even in the case where the amplitude of input AC voltage varies greatly. A transistor may be used as a rectifier element in such a way that a gate electrode of the transistor is connected to a second electrode of the transistor through a capacitor, and the potential of the gate electrode is held to be higher than the potential of the second electrode by a difference greater than or equal to the threshold voltage.

Abstract: While the supply of power is stopped, a data signal that has been held in a volatile memory section can be held in a nonvolatile memory section. In the nonvolatile memory section, a transistor having an extremely low off-state current allows a data signal to be held in the capacitor for a long period of time. Thus, the nonvolatile memory section can hold the logic state even while the supply of power is stopped. When the supply of power is started again, the data signal that has been held in the capacitor while the supply of power has been stopped is set at such a potential that malfunction does not occur by turning on the reset circuit.

Abstract: A storage circuit includes a volatile storage portion in which storage of a data signal is controlled by a clock signal and an inverted clock signal, and a nonvolatile storage portion in which a data signal supplied to the volatile storage portion can be held even after supply of power supply voltage is stopped. A wiring which supplies a power supply voltage and is connected to a protective circuit provided for a wiring for supplying the clock signal is provided separately from a wiring which supplies a power supply voltage and which is connected to the storage circuit. The timing of stop and restart of supply of the power supply voltage supplied to the wiring which is connected to the protective circuit is different from that of stop and restart of supply of the power supply voltage supplied to the wiring which is connected to the storage circuit.

Abstract: A semiconductor device with low power consumption and a small area is provided. By using a transistor including an oxide semiconductor for a channel as a transistor included in a flip-flop circuit, a divider circuit in which the number of transistors is small, power consumption is low, and the area is small can be achieved. By using the divider circuit, a semiconductor device which operates stably and is highly reliable can be provided.

Abstract: To provide a nonvolatile memory circuit having a novel structure. A first memory circuit, a second memory circuit, a first switch, a second switch, and a phase inverter circuit are included. The first memory circuit includes a first transistor formed using an oxide semiconductor film, a second transistor, a third transistor, and a capacitor. The first transistor formed using an oxide semiconductor film and the capacitor are used to form the nonvolatile memory circuit. Reductions in number of power supply lines and signal lines which are connected to the memory circuit and transistors used in the memory circuit allow a reduction in circuit scale of the nonvolatile memory circuit.

Abstract: A signal processing circuit using a nonvolatile memory circuit with a novel structure is provided. The nonvolatile memory circuit is formed using a transistor including an oxide semiconductor and a capacitor connected to one of a source electrode and a drain electrode of the transistor. A high-level potential is written to the memory circuit in advance, and this state is kept in the case where data to be saved has a high-level potential, whereas a low-level potential is written to the memory circuit in the case where data to be saved has a low-level potential. Thus, a signal processing circuit with improved writing speed can be provided.

Abstract: A flip-flop circuit consuming lower power than a conventional flip-flop circuit is provided. Further, a flip-flop circuit having a smaller number of transistors than a conventional flip-flop circuit to have a reduced footprint is provided. An n-channel transistor is used as a transistor which is to be turned on at a high level potential and a p-channel transistor is used as a transistor which is to be turned on at a low level potential, whereby the flip-flop circuit can operate only with a clock signal and without an inverted signal of the clock signal, and the number of transistors that operate only with a clock signal in the flip-flop circuit can be reduced.

Abstract: To provide a storage device with low power consumption. The storage device includes a plurality of cache lines. Each of the cache lines includes a data field which stores cache data; a tag which stores address data corresponding the cache data; and a valid bit which stores valid data indicating whether the cache data stored in the data field is valid or invalid. Whether power is supplied to the tag and the data field in each of the cache lines is determined based on the valid data stored in the valid bit.

Abstract: A structure capable of changing the characteristic value of an element after the formation of the element in order to prevent the increase of the manufacturing cost and delay in the delivery of a product. A plurality of diodes is connected in series. Then, a part of the plurality of diodes is short-circuited by a wiring. In specific, a diode and a wiring are connected in parallel, whereby a current flows preferentially into the wiring, so that the diode can be regarded as nonexistent. Then, the wiring is cut at a part of the wiring, thereby having the diode which is connected to the wiring in parallel before the cutting functioning.

Abstract: To provide a highly reliable semiconductor device (an RF tag) which operates normally even when a communication distance is extremely short, a protection circuit (a limiter circuit) for protecting an element which forms a semiconductor device (an RF tag) capable of wirelessly communicating data is provided. When the DC power supply potential which is generated in a rectifier circuit is equal to or greater than a predetermined value (a reference value), the protection circuit is made to operate, and the value of the generated DC power supply potential is reduced. On the other hand, when the DC power supply potential which is generated in the rectifier circuit is equal to or less than the predetermined value (reference value), the protection circuit is made not to operate, and the value of the generated DC power supply potential is used without change.

Abstract: An object is to provide a semiconductor device which operates stably even when the communication distance between a reader/writer and a non-contact data carrier is largely changed. A protection circuit is provided in the non-contact data carrier, and an operating state and a non-operating state of the protection circuit are switched depending on the communication distance between the reader/writer and the non-contact data carrier. The operating point at which the operating state and the non-operating state of the protection circuit are switched is different between the case where input voltage of the protection circuit is low in an initial state and then gradually raised and the case where input voltage of the protection circuit is high in an initial state and then gradually lowered.

Abstract: A semiconductor device with low power consumption and a small area is provided. By using a transistor including an oxide semiconductor for a channel as a transistor included in a flip-flop circuit, a divider circuit in which the number of transistors is small, power consumption is low, and the area is small can be achieved. By using the divider circuit, a semiconductor device which operates stably and is highly reliable can be provided.

Abstract: An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

Abstract: To provide a nonvolatile memory circuit having a novel structure. A first memory circuit, a second memory circuit, a first switch, a second switch, and a phase inverter circuit are included. The first memory circuit includes a first transistor formed using an oxide semiconductor film, a second transistor, a third transistor, and a capacitor. The first transistor formed using an oxide semiconductor film and the capacitor are used to form the nonvolatile memory circuit. Reductions in number of power supply lines and signal lines which are connected to the memory circuit and transistors used in the memory circuit allow a reduction in circuit scale of the nonvolatile memory circuit.

Abstract: When a CPU provided with a latch memory is operated, a constant storage method or an end storage method is selected depending on what is processed by the CPU; thus, the CPU provided with a latch memory has low power consumption. When the CPU provided with a latch memory is operated, in the case where the number of times of turning on and off the power source is high, a constant storage method is employed and in the case where the number of times of turning on and off the power source is low, an end storage method is employed. Whether a constant storage method or an end storage method is selected is determined based on the threshold value set depending on power consumption.

Abstract: A signal processing circuit using a nonvolatile memory circuit with a novel structure is provided. The nonvolatile memory circuit is formed using a transistor including an oxide semiconductor and a capacitor connected to one of a source electrode and a drain electrode of the transistor. A high-level potential is written to the memory circuit in advance, and this state is kept in the case where data to be saved has a high-level potential, whereas a low-level potential is written to the memory circuit in the case where data to be saved has a low-level potential. Thus, a signal processing circuit with improved writing speed can be provided.

Abstract: A storage circuit includes a volatile storage portion in which storage of a data signal is controlled by a clock signal and an inverted clock signal, and a nonvolatile storage portion in which a data signal supplied to the volatile storage portion can be held even after supply of power supply voltage is stopped. A wiring which supplies a power supply voltage and is connected to a protective circuit provided for a wiring for supplying the clock signal is provided separately from a wiring which supplies a power supply voltage and which is connected to the storage circuit. The timing of stop and restart of supply of the power supply voltage supplied to the wiring which is connected to the protective circuit is different from that of stop and restart of supply of the power supply voltage supplied to the wiring which is connected to the storage circuit.

Abstract: The semiconductor memory device includes an initialization memory cell having a first inverter circuit including a first transistor and a second transistor, and a second inverter circuit whose input portion is connected to an output portion of the first inverter circuit and output portion is connected to an input portion of the first inverter circuit, and including a third transistor and a fourth transistor. An absolute value of a threshold voltage of the third transistor is smaller than that of the first transistor.