Patents by Inventor Masashi Fujita

Masashi Fujita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120206956
    Abstract: While the supply of power is stopped, a data signal that has been held in a volatile memory section can be held in a nonvolatile memory section. In the nonvolatile memory section, a transistor having an extremely low off-state current allows a data signal to be held in the capacitor for a long period of time. Thus, the nonvolatile memory section can hold the logic state even while the supply of power is stopped. When the supply of power is started again, the data signal that has been held in the capacitor while the supply of power has been stopped is set at such a potential that malfunction does not occur by turning on the reset circuit.
    Type: Application
    Filed: February 3, 2012
    Publication date: August 16, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Masashi Fujita
  • Publication number: 20120195115
    Abstract: A first field-effect transistor provided over a substrate in which an insulating region is provided over a first semiconductor region and a second semiconductor region is provided over the insulating region; an insulating layer provided over the substrate; a second field-effect transistor that is provided one flat surface of the insulating layer and includes an oxide semiconductor layer; and a control terminal are provided. The control terminal is formed in the same step as a source and a drain of the second field-effect transistor, and a voltage for controlling a threshold voltage of the first field-effect transistor is supplied to the control terminal.
    Type: Application
    Filed: January 24, 2012
    Publication date: August 2, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Masashi Fujita, Yutaka Shionoiri, Hiroyuki Tomatsu, Hidetomo Kobayashi
  • Patent number: 8174229
    Abstract: The present invention provides a stage apparatus capable of reducing a positioning time without increasing a positional deviation. A positioning control method of a sample stage apparatus includes: a high-speed movement step of moving a table to a high-speed movement target position at a first movement speed; a positional deviation correcting step of moving the table to a low-speed positioning step start position at a second movement speed that is lower than the first movement speed; a low-speed positioning step of moving the table to a target position at a third movement speed that is lower than the second movement speed. After the low-speed positioning step is completed, a rod connected to a motor returns to its original position to separate a pin of the rod side from a concave portion of the table side.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: May 8, 2012
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Masashi Fujita, Shuichi Nakagawa, Takashi Kobayashi
  • Patent number: 8164933
    Abstract: A semiconductor device is provided, which comprises a rectifier circuit configured to generate a first voltage from a first signal inputted from an input terminal, a comparing circuit configured to compare a reference voltage and the first voltage inputted from the rectifier circuit and to output a second signal to a switch, and a voltage generation circuit configured to generate a second voltage from the first signal inputted from the input terminal. The rectifier circuit includes a transistor including at least a control terminal, and the voltage generation circuit inputs the second voltage to the control terminal when the switch is turned on in accordance with the second signal.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: April 24, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Fujita, Kiyoshi Kato
  • Publication number: 20120075897
    Abstract: An object is to provide a rectifier circuit of which the drop in the output voltage by the threshold voltage of a transistor used as a rectifier element is suppressed. Another object is to provide a rectifier circuit whose variations in the output voltage are suppressed even in the case where the amplitude of input AC voltage varies greatly. A transistor may be used as a rectifier element in such a way that a gate electrode of the transistor is connected to a second electrode of the transistor through a capacitor, and the potential of the gate electrode is held to be higher than the potential of the second electrode by a difference greater than or equal to the threshold voltage.
    Type: Application
    Filed: September 15, 2011
    Publication date: March 29, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Masashi FUJITA
  • Publication number: 20110261588
    Abstract: An inverter module and an integrated-inverter electric compressor using the same, which can eliminate noise interference, noise leakage, and the like attributable to a smoothing capacitor accommodated therein and which can be reduced in size and weight is provided. An inverter module (11) includes a resin module case (17); a power system board (15) provided on a bottom side of the module case (17); and a control board (19) provided on an upper side of the module case (17). A smoothing capacitor (18) connected to a power supply line for the power system board (15) is incorporated into the module case (17), and the smoothing capacitor (18) is electromagnetically shielded with respect to the power system board (15) and the control board (19).
    Type: Application
    Filed: June 2, 2010
    Publication date: October 27, 2011
    Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Makoto Hattori, Hidetaka Sato, Takashi Nakagami, Kazunori Teshima, Mitsuaki Arita, Masashi Fujita
  • Patent number: 8036604
    Abstract: An object is to provide a circuit configuration with which the number of transistors can be reduced and power conversion efficiency can be prevented from being reduced, in a transmitting and receiving circuit. The transmitting and receiving circuit includes a voltage doubler rectifier circuit having N stages, each of which includes a capacitor, where N is a positive integer. The voltage doubler rectifier circuit having N stages is connected to a circuit having a modulation function. In the capacitor in any one of the N stages, one electrode of the one capacitor is connected to an input terminal of the transmitting and receiving circuit, and a node to which the other electrode of the one capacitor is connected is connected to a circuit having a demodulation function. Since the transmitting and receiving circuit can be formed of fewer transistors, it can be reduced in size. Since a reduction in power conversion efficiency can be prevented, a power supply potential can be efficiently generated.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: October 11, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Fujita, Yutaka Shionoiri
  • Publication number: 20110188296
    Abstract: The semiconductor memory device includes an initialization memory cell having a first inverter circuit including a first transistor and a second transistor, and a second inverter circuit whose input portion is connected to an output portion of the first inverter circuit and output portion is connected to an input portion of the first inverter circuit, and including a third transistor and a fourth transistor. An absolute value of a threshold voltage of the third transistor is smaller than that of the first transistor.
    Type: Application
    Filed: April 14, 2011
    Publication date: August 4, 2011
    Inventor: Masashi Fujita
  • Patent number: 7929332
    Abstract: The semiconductor memory device includes an initialization memory cell having a first inverter circuit including a first transistor and a second transistor, and a second inverter circuit whose input portion is connected to an output portion of the first inverter circuit and output portion is connected to an input portion of the first inverter circuit, and including a third transistor and a fourth transistor. An absolute value of a threshold voltage of the third transistor is smaller than that of the first transistor.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: April 19, 2011
    Assignee: Semiconductor Energy laboratory Co., Ltd.
    Inventor: Masashi Fujita
  • Patent number: 7901521
    Abstract: An aluminum base alloy is produced by supercooling a molten alloy composed mainly of aluminum. The molten alloy contains an element capable of forming a quasicrystalline phase, an element which aids formation of the quasicrystals, and an element which stabilizes a supercooled state of the molten alloy and delays crystallization of a crystalline phase, and is composed of a mixed composition of a fine amorphous phase and an aluminum crystalline phase or an aluminum supersaturated solid solution phase, or a single phase of only an amorphous phase.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: March 8, 2011
    Assignee: Honda Motor Co., Ltd.
    Inventors: Masashi Fujita, Akihisa Inoue, Hisamichi Kimura
  • Patent number: 7900896
    Abstract: An object of the present invention is to provide a specimen stage which is simple in structure, and which suppresses a positional shift due to a friction heat caused by a brake or the like. One aspect to achieve the object provides a specimen stage including: a thrust portion thrust by a thrusting member; and a slide surface thrust by the thrust portion. When the specimen stage stops, the specimen stage performs a control in a way that a part of the slide surface in contact with the thrust portion, and/or a portion adjacent to the part or the thrust portion is heated. By heating the part of the slide surface or the like in this manner, a temperature gradient can be suppressed as described above (see FIG. 3).
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: March 8, 2011
    Assignee: Hitachi High-Technologies Corporation
    Inventor: Masashi Fujita
  • Publication number: 20100243744
    Abstract: An object is to provide a semiconductor device which operates stably even when the communication distance between a reader/writer and a non-contact data carrier is largely changed. A protection circuit is provided in the non-contact data carrier, and an operating state and a non-operating state of the protection circuit are switched depending on the communication distance between the reader/writer and the non-contact data carrier. The operating point at which the operating state and the non-operating state of the protection circuit are switched is different between the case where input voltage of the protection circuit is low in an initial state and then gradually raised and the case where input voltage of the protection circuit is high in an initial state and then gradually lowered.
    Type: Application
    Filed: March 26, 2010
    Publication date: September 30, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Masashi FUJITA
  • Patent number: 7782657
    Abstract: A cache memory having valid bits, where a circuit configuration in a memory cell of a valid bit is improved so as to perform invalidation at high speed. The invention provides a cache memory including a memory cell that has a function to perform invalidation at high speed. One mode of the invention is a semiconductor device including a memory cell of a valid bit, where two inverters are connected in series to form a loop, a drain of an N-channel transistor is connected to an output signal line of one of the inverters, a gate thereof is connected to a reset signal line of a CPU, and a source thereof is connected to a ground line. The initial value of the memory cell is determined by inputting a reset signal of the CPU to the gate.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: August 24, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Fujita, Yoshiyuki Kurokawa
  • Publication number: 20100096736
    Abstract: A structure capable of changing the characteristic value of an element after the formation of the element in order to prevent the increase of the manufacturing cost and delay in the delivery of a product. A plurality of diodes is connected in series. Then, a part of the plurality of diodes is short-circuited by a wiring. In specific, a diode and a wiring are connected in parallel, whereby a current flows preferentially into the wiring, so that the diode can be regarded as nonexistent. Then, the wiring is cut at a part of the wiring, thereby having the diode which is connected to the wiring in parallel before the cutting functioning.
    Type: Application
    Filed: October 12, 2009
    Publication date: April 22, 2010
    Inventors: Asami Tadokoro, Masashi Fujita
  • Publication number: 20100079921
    Abstract: To provide a highly reliable semiconductor device (an RF tag) which operates normally even when a communication distance is extremely short, a protection circuit (a limiter circuit) for protecting an element which forms a semiconductor device (an RF tag) capable of wirelessly communicating data is provided. When the DC power supply potential which is generated in a rectifier circuit is equal to or greater than a predetermined value (a reference value), the protection circuit is made to operate, and the value of the generated DC power supply potential is reduced. On the other hand, when the DC power supply potential which is generated in the rectifier circuit is equal to or less than the predetermined value (reference value), the protection circuit is made not to operate, and the value of the generated DC power supply potential is used without change.
    Type: Application
    Filed: September 29, 2009
    Publication date: April 1, 2010
    Inventor: Masashi Fujita
  • Publication number: 20090251091
    Abstract: The present invention provides a stage apparatus capable of reducing a positioning time without increasing a positional deviation. A positioning control method of a sample stage apparatus includes: a high-speed movement step of moving a table to a high-speed movement target position at a first movement speed; a positional deviation correcting step of moving the table to a low-speed positioning step start position at a second movement speed that is lower than the first movement speed; a low-speed positioning step of moving the table to a target position at a third movement speed that is lower than the second movement speed. After the low-speed positioning step is completed, a rod connected to a motor returns to its original position to separate a pin of the rod side from a concave portion of the table side.
    Type: Application
    Filed: April 8, 2009
    Publication date: October 8, 2009
    Inventors: Masashi FUJITA, Shuichi NAKAGAWA, Takashi KOBAYASHI
  • Publication number: 20090218510
    Abstract: An object of the present invention is to provide a specimen stage which is simple in structure, and which suppresses a positional shift due to a friction heat caused by a brake or the like. One aspect to achieve the object provides a specimen stage including: a thrust portion thrust by a thrusting member; and a slide surface thrust by the thrust portion. When the specimen stage stops, the specimen stage performs a control in a way that a part of the slide surface in contact with the thrust portion, and/or a portion adjacent to the part or the thrust portion is heated. By heating the part of the slide surface or the like in this manner, a temperature gradient can be suppressed as described above (see FIG. 3).
    Type: Application
    Filed: February 26, 2009
    Publication date: September 3, 2009
    Inventor: MASASHI FUJITA
  • Patent number: 7541719
    Abstract: Provided is a stage on which to place a sample, which is capable of performing a high-precision positioning at a short time, and which prevents an image drift of a measuring object. The stage includes: a base having a guiding unit; a table which moves in a movement direction along the guiding unit; a motion unit which provides motion in the movement direction in order to cause the table to move; and a transmission unit for transmitting the motion to the table. In the stage, the transmission unit includes a table block fixed to the table, and a motion block fixed to the motion unit; and the table block and the motion block contact each other at two points forward and backward in the movement direction while in motion, and are separated away from each other while not in motion.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: June 2, 2009
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Masashi Fujita, Shuichi Nakagawa
  • Publication number: 20090116278
    Abstract: A cache memory having valid bits, where a circuit configuration in a memory cell of a valid bit is improved so as to perform invalidation at high speed. The invention provides a cache memory including a memory cell that has a function to perform invalidation at high speed. One mode of the invention is a semiconductor device including a memory cell of a valid bit, where two inverters are connected in series to form a loop, a drain of an N-channel transistor is connected to an output signal line of one of the inverters, a gate thereof is connected to a reset signal line of a CPU, and a source thereof is connected to a ground line. The initial value of the memory cell is determined by inputting a reset signal of the CPU to the gate.
    Type: Application
    Filed: October 1, 2008
    Publication date: May 7, 2009
    Inventors: Masashi Fujita, Yoshiyuki Kurokawa
  • Patent number: 7528327
    Abstract: It is an object to provide an inspection method to enable simple and easy inspection of the electrical connecting state between a connecting terminal of a semiconductor integrated circuit over a substrate such as a glass substrate or a plastic substrate and a crimp connecting terminal of a flexible printed circuit. A crimp inspection terminal is provided to a flexible printed circuit so as to inspect all connecting terminals of the semiconductor integrated circuit over the substrate. A crimp connecting terminal and a crimp inspection terminal are connected with one connecting terminal of the semiconductor integrated circuit by thermocompression. By such a configuration, the inspection of the electrical connecting state between the connecting terminal and the crimp inspection terminal, in the other words, the inspection of conducting state can be performed by using only an external connecting terminal of the flexible printed circuit through the crimp inspection terminal.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: May 5, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Masashi Fujita