Patents by Inventor Min Yuan

Min Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190003044
    Abstract: Surfaces, articles, and processes having silicon-nitride-containing thermal chemical vapor deposition coating are disclosed. A process includes producing a silicon-nitride-containing thermal chemical vapor deposition coating on a surface within a chamber. Flow into and from the chamber is restricted or halted during the producing of the silicon-nitride-containing thermal chemical vapor deposition coating on the surface. A surface includes a silicon-nitride-containing thermal chemical vapor deposition coating. The surface has at least a concealed portion that is obstructed from view. An article includes a silicon-nitride-containing thermal chemical vapor deposition coating on a surface within a chamber. The surface has at least a concealed portion that is obstructed from view.
    Type: Application
    Filed: September 5, 2018
    Publication date: January 3, 2019
    Inventors: Min YUAN, James B. MATTZELA, David A. SMITH
  • Patent number: 10107737
    Abstract: An apparatus and a method for evaluating film adhesion are disclosed. The film is disposed on a first substrate, a side of the first substrate provided with the film is attached to a second substrate, and the film is divided into units. The apparatus includes an evaluation machine, which includes an upper fixing mechanism and a lower fixing mechanism disposed opposite to each other, the second substrate is detachably fixed on the upper fixing mechanism, and a side of the first substrate not provided with the film is detachably fixed on the lower fixing mechanism. The evaluation machine further includes a force application device, which is configured to apply an external force to the upper fixing mechanism and/or the lower fixing mechanism, so that the upper fixing mechanism and the lower fixing mechanism generate relative movement away from each other.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 23, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Min Yuan, Hongwei Xing, Guilin Liu
  • Patent number: 10087521
    Abstract: Surfaces, articles, and processes having silicon-nitride-containing thermal chemical vapor deposition coating are disclosed. A process includes producing a silicon-nitride-containing thermal chemical vapor deposition coating on a surface within a chamber. Flow into and from the chamber is restricted or halted during the producing of the silicon-nitride-containing thermal chemical vapor deposition coating on the surface. A surface includes a silicon-nitride-containing thermal chemical vapor deposition coating. The surface has at least a concealed portion that is obstructed from view. An article includes a silicon-nitride-containing thermal chemical vapor deposition coating on a surface within a chamber. The surface has at least a concealed portion that is obstructed from view.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: October 2, 2018
    Assignee: SILCOTEK CORP.
    Inventors: Min Yuan, James B. Mattzela, David A. Smith
  • Publication number: 20180144082
    Abstract: A method of designing a layout includes identifying a cell having a cell height being a non-integral multiple of a minimum pitch, generating, using a processor, possibilities of an ordered arrangement of a plurality of virtual grid lines parallel to the top boundary and the bottom boundary, and placing at least two conductive patterns on the plurality of virtual grid lines. The cell height is defined by a top boundary and a bottom boundary, and the minimum pitch is based on a manufacturing process. The plurality of virtual grid lines are separated from each other by a plurality of spacings, and the top boundary overlaps a first virtual grid line of the plurality of virtual grid lines and the bottom boundary overlaps a second virtual grid line of the plurality of virtual grid lines. At least one spacing is different from another spacing of the plurality of spacings.
    Type: Application
    Filed: November 18, 2016
    Publication date: May 24, 2018
    Inventors: Mahantesh HANCHINAL, Chi Wei HU, Min-Yuan TSAI, Shu-Yi YING
  • Patent number: 9915001
    Abstract: A chemical vapor deposition process and coated article are disclosed. The chemical vapor deposition process includes positioning an article in a chemical vapor deposition chamber, then introducing a deposition gas to the chemical vapor deposition chamber at a sub-decomposition temperature that is below the thermal decomposition temperature of the deposition gas, and then heating the chamber to a super-decomposition temperature that is equal to or above the thermal decomposition temperature of the deposition gas resulting in a deposited coating on at least a surface of the article from the introducing of the deposition gas. The chemical vapor deposition process remains within a pressure range of 0.01 psia and 200 psia and/or the deposition gas is dimethylsilane. The coated article includes a substrate subject to corrosion and a deposited coating on the substrate, the deposited coating having silicon, and corrosion resistance.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: March 13, 2018
    Assignee: Silcotek Corp.
    Inventors: Min Yuan, David A. Smith, Paul H. Silvis, James B. Mattzela
  • Publication number: 20180002500
    Abstract: Disclosed are a reinforcing fiber bundle composed of a carbon fiber bundle treated with an emulsion; a carbon fiber reinforced thermoplastic resin molded body using the same; and a method for producing a reinforcing fiber bundle; wherein the emulsion contains a modified polyolefin (A1) comprising at least a metal carboxylate bonded to the polymer chain, and 0.1 to 5,000 moles of an amine compound (B) represented by the following general formula (1), per one mole of the carboxylate group in the modified polyolefin (A1); R—NH2??(1) wherein the formula (1), R is a hydrogen atom or a hydrocarbon group having 1 to 10 carbon atoms.
    Type: Application
    Filed: January 14, 2016
    Publication date: January 4, 2018
    Applicants: MITSUI CHEMICALS, INC., FORMOSA PLASTICS CORPORATION
    Inventors: Naoshi NAGAI, Takeharu ISAKI, Masaki SHIMIZU, Junichi ISHIKAWA, Kazuaki KIKUCHI, Yi-Chuan CHANG, Kai-Cheng YEN, Min-Yuan LIN
  • Patent number: 9852989
    Abstract: Power grids of an IC are provided. A power grid includes first power traces disposed in a first metal layer and parallel to a first direction, second power traces disposed in a second metal layer and parallel to a second direction that is perpendicular to the first direction, and third power traces disposed in the first metal layer parallel to the first direction. The first power traces arranged in the same straight line are separated from each other by a plurality of first gaps. The third power traces arranged in the same straight line are separated from each other by a plurality of second gaps. Each first gap is surrounded by the two adjacent third power traces. Each second gap is surrounded by the two adjacent first power traces. The first power traces are coupled to the third power traces via the second power traces.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: December 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Shen Lin, Min-Yuan Tsai, Kuo-Nan Yang, Chung-Hsing Wang
  • Publication number: 20170330899
    Abstract: A semiconductor device includes a bulk substrate of a first conductivity type, a first semiconductor on insulator (SOI) block in the bulk substrate, a first well of the first conductivity type in the first SOI block, a second well of a second conductivity type in the first SOI block, a first guard ring of the first conductivity type in the first SOI block around at least a portion of a periphery of the first SOI block, and a second guard ring of the second conductivity type in the first SOI block around at least a portion of the periphery of the first SOI block. The first conductivity type is different than the second conductivity type.
    Type: Application
    Filed: July 31, 2017
    Publication date: November 16, 2017
    Inventors: CHI-MIN YUAN, DAVID R. TIPPLE
  • Publication number: 20170320966
    Abstract: A humanized monoclonal antibody against the CD34 surface antigen is provided in the present disclosure. The humanized monoclonal antibody includes a light chain variable region and a heavy chain variable region. In which, a nucleotide sequence encoding the amino acid sequence for the light chain variable region comprises a nucleotide sequence which encodes the amino acid sequence of SEQ ID No. 9 or an amino acid sequence with at least 80% sequence identity to the sequence of SEQ ID No. 9, and a nucleotide sequence encoding the amino acid sequence for the heavy chain variable region comprises a nucleotide sequence which encodes the amino acid sequence of SEQ ID No. 10 or an amino acid sequence with at least 80% sequence identity to the sequence of SEQ ID No. 10.
    Type: Application
    Filed: May 8, 2017
    Publication date: November 9, 2017
    Applicant: Industrial Technology Research Institute
    Inventors: Chia-Yu FAN, Min-Yuan CHOU
  • Patent number: 9775267
    Abstract: A structure for reducing electromagnetic interference is provided, which includes a circuit board, an expansion slot and an electrical conductor. The circuit board has an upper surface and a ground circuit. The expansion slot is disposed on the upper surface of the circuit board, and has at least one metal pin electrically connected to the circuit board. The electrical conductor is located above the upper surface of the circuit board, and a gap is maintained between the electrical conductor and the metal pin of the expansion slot to produce a capacitor. A method for reducing electromagnetic interference is further provided, for accomplishing the above-mentioned structure.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: September 26, 2017
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Min-Yuan Yang, Chien-Hsiang Huang, Hsin-Hong Wu, Lien-Cheng Tsai
  • Patent number: 9754966
    Abstract: A semiconductor device includes a bulk substrate of a first conductivity type, a first semiconductor on insulator (SOI) block in the bulk substrate, a first well of the first conductivity type in the first SOI block, a second well of a second conductivity type in the first SOI block, a first guard ring of the first conductivity type in the first SOI block around at least a portion of a periphery of the first SOI block, and a second guard ring of the second conductivity type in the first SOI block around at least a portion of the periphery of the first SOI block. The first conductivity type is different than the second conductivity type.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: September 5, 2017
    Assignee: NXP USA, Inc.
    Inventors: Chi-Min Yuan, David R. Tipple
  • Patent number: 9719723
    Abstract: Disclosed is a substrate support structure, a vacuum drying apparatus and a method for vacuum drying a substrate. The substrate support structure comprises: a support pin having a top end for supporting a substrate; and an auxiliary support assembly including: a drive device; a support rod driven by the drive device; and a support disc disposed at a top end of the support rod and made of flexible material adapted to support the substrate, wherein the drive device is configured to drive the support rod to move in a direction parallel to an axial direction of the support pin so as to make the support disc positioned below or above the top end of the support pin as the support rod moves, so that the substrate is selectively supported by the support disc or the support pin. The substrate support structure, the vacuum drying apparatus and the method for vacuum drying a substrate can prevent the substrate from being easily scratched and avoid poor quality and uneven brightness of the substrate.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: August 1, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Hongwei Xing, Huihui Mu, Min Yuan, Hequn Zhang, Longgen Yang
  • Publication number: 20170167015
    Abstract: Surfaces, articles, and processes having silicon-nitride-containing thermal chemical vapor deposition coating are disclosed. A process includes producing a silicon-nitride-containing thermal chemical vapor deposition coating on a surface within a chamber. Flow into and from the chamber is restricted or halted during the producing of the silicon-nitride-containing thermal chemical vapor deposition coating on the surface. A surface includes a silicon-nitride-containing thermal chemical vapor deposition coating. The surface has at least a concealed portion that is obstructed from view. An article includes a silicon-nitride-containing thermal chemical vapor deposition coating on a surface within a chamber. The surface has at least a concealed portion that is obstructed from view.
    Type: Application
    Filed: December 15, 2015
    Publication date: June 15, 2017
    Inventors: Min YUAN, James B. MATTZELA, David A. SMITH
  • Publication number: 20170130334
    Abstract: Thermal chemical vapor deposition split-functionalizing processes, coatings, and products are disclosed. The thermal chemical vapor deposition split-functionalizing process includes positioning an article within an enclosed chamber, functionalizing the article within a first temperature range for a first period of time, and then further functionalizing the article within a second temperature range for a second period of time. The thermal chemical vapor deposition split-functionalized product includes a functionalization formed by functionalizing within a first temperature range for a first period of time and a further functionalization formed by further functionalizing within a second temperature range for a second period of time.
    Type: Application
    Filed: November 5, 2015
    Publication date: May 11, 2017
    Inventors: Min YUAN, Paul H. SILVIS, David A. SMITH, James B. MATTZELA
  • Publication number: 20170034962
    Abstract: A structure for reducing electromagnetic interference is provided, which includes a circuit board, an expansion slot and an electrical conductor. The circuit board has an upper surface and a ground circuit. The expansion slot is disposed on the upper surface of the circuit board, and has at least one metal pin electrically connected to the circuit board. The electrical conductor is located above the upper surface of the circuit board, and a gap is maintained between the electrical conductor and the metal pin of the expansion slot to produce a capacitor. A method for reducing electromagnetic interference is further provided, for accomplishing the above-mentioned structure.
    Type: Application
    Filed: July 19, 2016
    Publication date: February 2, 2017
    Inventors: Min-Yuan Yang, Chien-Hsiang Huang, Hsin-Hong Wu, Lien-Cheng Tsai
  • Patent number: 9547742
    Abstract: A method for configuring a via in a semiconductor device includes determining time dependent dielectric breakdown failure rate as a function of distance between the via and a metal line, generating candidate via configurations with different sizes, rotation, and offset values for the via, determining TDDB failure rate for the candidate via configurations, and selecting one of the candidate via configurations with an optimal TDDB failure rate for the via.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: January 17, 2017
    Assignee: NXP USA, Inc.
    Inventor: Chi-Min Yuan
  • Publication number: 20160320124
    Abstract: Disclosed is a substrate support structure, a vacuum drying apparatus and a method for vacuum drying a substrate. The substrate support structure comprises: a support pin having a top end for supporting a substrate; and an auxiliary support assembly including: a drive device; a support rod driven by the drive device; and a support disc disposed at a top end of the support rod and made of flexible material adapted to support the substrate, wherein the drive device is configured to drive the support rod to move in a direction parallel to an axial direction of the support pin so as to make the support disc positioned below or above the top end of the support pin as the support rod moves, so that the substrate is selectively supported by the support disc or the support pin. The substrate support structure, the vacuum drying apparatus and the method for vacuum drying a substrate can prevent the substrate from being easily scratched and avoid poor quality and uneven brightness of the substrate.
    Type: Application
    Filed: April 1, 2016
    Publication date: November 3, 2016
    Inventors: Hongwei Xing, Huihui Mu, Min Yuan, Hequn Zhang, Longgen Yang
  • Publication number: 20160314238
    Abstract: A method for configuring a via in a semiconductor device includes determining time dependent dielectric breakdown failure rate as a function of distance between the via and a metal line, generating candidate via configurations with different sizes, rotation, and offset values for the via, determining TDDB failure rate for the candidate via configurations, and selecting one of the candidate via configurations with an optimal TDDB failure rate for the via.
    Type: Application
    Filed: April 27, 2015
    Publication date: October 27, 2016
    Inventor: Chi-Min Yuan
  • Patent number: 9471744
    Abstract: Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: October 18, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung Lung Lin, Chin-Chang Hsu, Min-Yuan Tsai, Wen-Ju Yang, Chien Lin Ho
  • Publication number: 20160289124
    Abstract: Thermal chemical vapor deposition products and processes are disclosed. The products include a ceramic substrate and a non-porous surface on the ceramic substrate, the non-porous surface including a ceramic material. The process includes transporting fluid along a non-porous surface, the non-porous surface being positioned on a ceramic substrate and being a thermal chemical vapor deposition coating.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 6, 2016
    Inventors: James B. MATTZELA, Min YUAN, David A. SMITH, Paul H. SILVIS