Abstract: A delivery device, manufacturing system, and process of manufacturing are disclosed. The delivery device includes a feed tube and a chemical vapor deposition coating applied over an inner surface of the feed tube, the chemical vapor deposition coating being formed from decomposition of dimethylsilane. The manufacturing system includes the delivery device and a chamber in selective fluid communication with the delivery device. The process of manufacturing uses the manufacturing system to produce an article.

Abstract: The present invention provides a photovoltaic device, such as, a solar cell, having a substrate and an absorber layer disposed on the substrate. The absorber layer includes a doped or undoped composition represented by the formula: Cu1-yIn1-xGaxSe2-zSz wherein 0?x?1; 0?y?0.15 and 0?z?2; wherein the absorber layer is formed by a solution-based deposition process which includes the steps of contacting hydrazine and a source of Cu, a source of In, a source of Ga, a source of Se, and optionally a source of S, and further optionally a source of a dopant, under conditions sufficient to produce a homogeneous solution; coating the solution on the substrate to produce a coated substrate; and heating the coated substrate to produce the photovoltaic device. A photovoltaic device and a process for making same based on a hydrazinium-based chalcogenide precursor are also provided.

Abstract: An immediate response low dropout regulation system includes a low dropout regulation unit, a tracking voltage generation unit, and a self-driving unit. The low dropout regulation unit is used for generating and outputting an inner output voltage according to a reference voltage. The tracking voltage generation unit is used for generating and outputting a tracking voltage according to the reference voltage. The self-driving unit is coupled to the low dropout regulation unit and the tracking voltage generation unit. When a voltage difference between the tracking voltage and the inner output voltage is greater than a constant times threshold voltage, the self-driving unit provides a compensation current to an output terminal of the low dropout regulation unit.

Abstract: A wireless communication apparatus includes a first antenna, an antenna driving circuit, a first medium, a second medium, and a second antenna. The antenna driving circuit drives the first antenna. The first medium is electrically connected between the first antenna and the antenna driving circuit. The second medium and the first medium are in energy coupling. The second antenna is electrically connected with the second medium.

Abstract: A chemical vapor deposition process and coated article are disclosed. The chemical vapor deposition process includes positioning an article in a chemical vapor deposition chamber, then introducing a deposition gas to the chemical vapor deposition chamber at a sub-decomposition temperature that is below the thermal decomposition temperature of the deposition gas, and then heating the chamber to a super-decomposition temperature that is equal to or above the thermal decomposition temperature of the deposition gas resulting in a deposited coating on at least a surface of the article from the introducing of the deposition gas. The chemical vapor deposition process remains within a pressure range of 0.01 psia and 200 psia and/or the deposition gas is dimethylsilane. The coated article includes a substrate subject to corrosion and a deposited coating on the substrate, the deposited coating having silicon, and corrosion resistance.

Abstract: An analog to digital converting apparatus and an initial method thereof are provided. The analog to digital converting apparatus includes a first and a second switching capacitor units, a circuit unit, a first and a second initialization switches, a third and a fourth capacitors and a logic buffer. The first and the second switching capacitor units respectively couple first capacitors and second capacitors to a first logic voltage, a second logic voltage or a first or a second input voltage according to a first control signal, and respectively generate a first and a second voltage. The circuit unit compares the first voltage and the second voltage to generate the first control signal. The first and the second initialization switches are respectively connected in series between the first and the second voltage and a common-mode endpoint. The logic buffer outputs the first or the second logic voltage to the common-mode endpoint.

Abstract: Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.

Abstract: A coated article is disclosed. The article includes a coating formed by thermal decomposition, oxidation then functionalization. The article is configured for a marine environment, the marine environment including fouling features. The coating is resistant to the fouling features. Additionally or alternatively, the article is a medical device configured for a protein-containing environment, the protein-containing environment including protein adsorption features. The coating is resistant to the protein adsorption features.

Abstract: Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.

Abstract: Provided herein is a method and computer program product for designing and/or simulating a biotechnology experiment in silico; and for providing and generating revenue from a customized list of one or more biotechnology products and/or services related to the in silico designed or simulated biotechnology experiment or the product of that experiment. In illustrative examples, the products and or services are indirectly related to a biomolecule designed by the in silico designed biotechnology experiment. In addition, provided herein is a method and computer system for generating revenue, that includes providing a customer with a first computer program product for designing or performing a biotechnology experiment in silico; and providing the customer with access to a purchase function for purchasing a second computer program product for designing or performing a biotechnology experiment in silico.

Abstract: A memory access circuit includes a write data circuit and a first write switch circuit. The write data circuit is used for receiving double data rate data or single data rate data, and outputting odd term data and even term data of adjusted double data rate data or adjusted single data rate data. The first write switch circuit is used for outputting the odd term data of the adjusted double data rate data to an odd block of a memory and outputting the even term data of the adjusted double data rate data to an even block of the memory when the write data circuit receives the double data rate data, and outputting the adjusted single data rate data to the even block or the odd block of the memory when the write data circuit receives the single data rate data.

Abstract: A layout system automatically generates via definitions for a routing tool based on manufacturability of vias based on the via definitions. A physical verification tool of the system applies a set of preliminary via definitions to an integrated circuit test design at each of a plurality of offsets from a plurality of via locations to generate a set of candidate via definitions. Candidate via definitions that violate one or more design rules are discarded. A hierarchy constructor tool ranks the resulting candidate via definitions based on a combination of their manufacturability and frequency of applicability in the test design, and a predefined number of the candidate via definitions are selected based on their ranking. These selected via definitions can be used by a routing tool to generate a layout for another (non-test) integrated circuit device.

Abstract: A video output system at least includes a first video output terminal, a control circuit, a first digital-to-analog converter, and a first bias voltage generator. The first video output terminal is selectively connected with a first video input terminal of a display device through a signal cable. According to a constant detecting current generated by the first digital-to-analog converter, or the first bias voltage generator, the first video output terminal has a detecting voltage for indicating whether the video output system is connected with the display device. When the video output system is connected with the display device, the control circuit enables the first digital-to-analog converter but disables the first bias voltage generator. When the video output system is not connected with the display device, the control circuit disables the first digital-to-analog converter but enables the first bias voltage generator.

Abstract: An electronic device including an audio module, a monitoring module and a fan is provided. The audio module generates an audio signal and an audio parameter according to audio data, and transmits the audio signal to a play device. Furthermore, the monitoring module determines a speed of fan rotation base on the type of the play device, the audio parameter and a sensed temperature. Then, a rotation speed of the fan is adjusted according to the determined speed of fan rotation.

Abstract: A novel humanized antibody against the CD34 surface antigen on the human stem cells is provided. The humanized antibody contains a heavy chain variable region comprising an amino sequence as set forth in SEQ ID No. 1 and a light chain variable region comprising an amino sequence as set forth in SEQ ID No. 2. The disclosure also provides the applications of the disclosed humanized antibody.

Abstract: Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.

Abstract: Techniques for improving energy conversion efficiency in photovoltaic devices are provided. In one aspect, an antimony (Sb)-doped film represented by the formula, Cu1-yIn1-xGaxSbzSe2-wSw, provided, wherein: 0?x?1, and ranges therebetween; 0?y?0.2, and ranges therebetween; 0.001?z?0.02, and ranges therebetween; and 0?w?2, and ranges therebetween. A photovoltaic device incorporating the Sb-doped CIGS film and a method for fabrication thereof are also provided.

Abstract: A method of decomposing a layout for triple pattern lithography generates a first conflict graph from the layout. The method generates a second conflict graph from the first conflict graph, and identifies loops in the second conflict graph as decomposition violations.

Abstract: A method embodiment includes identifying an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins and outside a minimum spacing boundary, applying a grid map over the empty region, wherein the grid map comprises a plurality of grids inside the empty region, and filling the empty region with a plurality of dummy fin cells by placing a dummy fin cell in each of the plurality of grids, wherein applying the grid map and filling the empty region is performed using a computer.

Abstract: A method of inhibiting, preventing, or reducing damage to non-cancerous cells in a human subject during chemotherapeutic treatment or radiation treatment of cancer cells in the human subject includes administering to the human subject arsenic and/or one or more compounds of arsenic in a therapeutically effective amount prior to treatment with radiation or one or more chemotherapeutic agents.